Magnetic-field-to-digital converter using PWM and TDC techniques

C. H. Kuo; S. L. Chen; S. I. Liu

doi:10.1049/ip-cds:20045168

Magnetic-field-to-digital converter using PWM and TDC techniques

C. H. Kuo^*, S. L. Chen, S. I. Liu

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

A high resolution magnetic-field-to-digital converter (MDC) is presented. It is composed of a magnetic-field-to-pulse width converter (MPC), a cyclic pulse-shrinking time-to-digital converter (TDC) and a polarity detector. This prototype circuit has been fabricated in a 0.5μm CMOS DPDM process. With a clock rate of 16.6kHz, the power consumption is 42.5mW under 5V supply voltage. The equivalent resolution less than 16μT can be achieved within the range of ±10mT. After off-line calibration, the remaining offset is 0.017mT and its gain error is smaller than 0.4.

Original language	English
Pages (from-to)	247-252
Number of pages	6
Journal	IEE Proceedings: Circuits, Devices and Systems
Volume	153
Issue number	3
DOIs	https://doi.org/10.1049/ip-cds:20045168
Publication status	Published - 2006 Jun
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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abstract = "A high resolution magnetic-field-to-digital converter (MDC) is presented. It is composed of a magnetic-field-to-pulse width converter (MPC), a cyclic pulse-shrinking time-to-digital converter (TDC) and a polarity detector. This prototype circuit has been fabricated in a 0.5μm CMOS DPDM process. With a clock rate of 16.6kHz, the power consumption is 42.5mW under 5V supply voltage. The equivalent resolution less than 16μT can be achieved within the range of ±10mT. After off-line calibration, the remaining offset is 0.017mT and its gain error is smaller than 0.4.",

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AU - Kuo, C. H.

AU - Chen, S. L.

AU - Liu, S. I.

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Y1 - 2006/6

N2 - A high resolution magnetic-field-to-digital converter (MDC) is presented. It is composed of a magnetic-field-to-pulse width converter (MPC), a cyclic pulse-shrinking time-to-digital converter (TDC) and a polarity detector. This prototype circuit has been fabricated in a 0.5μm CMOS DPDM process. With a clock rate of 16.6kHz, the power consumption is 42.5mW under 5V supply voltage. The equivalent resolution less than 16μT can be achieved within the range of ±10mT. After off-line calibration, the remaining offset is 0.017mT and its gain error is smaller than 0.4.

AB - A high resolution magnetic-field-to-digital converter (MDC) is presented. It is composed of a magnetic-field-to-pulse width converter (MPC), a cyclic pulse-shrinking time-to-digital converter (TDC) and a polarity detector. This prototype circuit has been fabricated in a 0.5μm CMOS DPDM process. With a clock rate of 16.6kHz, the power consumption is 42.5mW under 5V supply voltage. The equivalent resolution less than 16μT can be achieved within the range of ±10mT. After off-line calibration, the remaining offset is 0.017mT and its gain error is smaller than 0.4.

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JF - IEE Proceedings: Circuits, Devices and Systems

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Magnetic-field-to-digital converter using PWM and TDC techniques

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