Low-threshold-voltage TaN/Ir/LaTiO p-MOSFETs incorporating low-temperature-formed shallow junctions

S. H. Lin, C. H. Cheng, W. B. Chen, F. S. Yeh, Albert Chin

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

We demonstrate a low threshold voltage (Vt) of -0.17 V and good hole mobility (54 cm2/V · s at 0.8 MV/cm) in TaN/ Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO2-covered Ni/Ga which reduced the high-κ dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.

Original languageEnglish
Pages (from-to)681-863
Number of pages183
JournalIEEE Electron Device Letters
Volume30
Issue number6
DOIs
Publication statusPublished - 2009

Keywords

  • LaTiO
  • Low V
  • Solid-phase diffusion (SPD)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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