Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance

Yu Chien Chiu; Chun Hu Cheng; Chun Yen Chang; Min Hung Lee; Hsiao Hsuan Hsu; Shiang Shiou Yen

doi:10.1109/VLSIT.2015.7223671

Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 10¹⁶ endurance

Yu Chien Chiu, Chun Hu Cheng, Chun Yen Chang, Min Hung Lee, Hsiao Hsuan Hsu, Shiang Shiou Yen

Undergraduate Program of Electro-Optical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

53 Citations (Scopus)

Abstract

In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10^-15 A/μm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔV_T window of 2.8V, fast 20-ns speed, 10³s retention at 85°C, and long extrapolated 10¹⁶ endurance at 85°C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.

Original language	English
Title of host publication	2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	T184-T185
ISBN (Electronic)	9784863485013
DOIs	https://doi.org/10.1109/VLSIT.2015.7223671
Publication status	Published - 2015 Aug 25
Event	Symposium on VLSI Technology, VLSI Technology 2015 - Kyoto, Japan Duration: 2015 Jun 16 → 2015 Jun 18

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2015-August
ISSN (Print)	0743-1562

Other

Other	Symposium on VLSI Technology, VLSI Technology 2015
Country/Territory	Japan
City	Kyoto
Period	2015/06/16 → 2015/06/18

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/VLSIT.2015.7223671

Cite this

Chiu, Y. C., Cheng, C. H., Chang, C. Y., Lee, M. H., Hsu, H. H., & Yen, S. S. (2015). Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 10¹⁶ endurance. In 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers (pp. T184-T185). Article 7223671 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2015.7223671

Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 10¹⁶ endurance. / Chiu, Yu Chien; Cheng, Chun Hu; Chang, Chun Yen et al.
2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. p. T184-T185 7223671 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chiu, YC, Cheng, CH, Chang, CY, Lee, MH, Hsu, HH & Yen, SS 2015, Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 10¹⁶ endurance. in 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers., 7223671, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. T184-T185, Symposium on VLSI Technology, VLSI Technology 2015, Kyoto, Japan, 2015/06/16. https://doi.org/10.1109/VLSIT.2015.7223671

Chiu YC, Cheng CH, Chang CY, Lee MH, Hsu HH, Yen SS. Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 10¹⁶ endurance. In 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2015. p. T184-T185. 7223671. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2015.7223671

Chiu, Yu Chien ; Cheng, Chun Hu ; Chang, Chun Yen et al. / Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 10¹⁶ endurance. 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. pp. T184-T185 (Digest of Technical Papers - Symposium on VLSI Technology).

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abstract = "In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10-15 A/μm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔVT window of 2.8V, fast 20-ns speed, 103s retention at 85°C, and long extrapolated 1016 endurance at 85°C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.",

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