Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance

Yu Chien Chiu, Chun Hu Cheng, Chun Yen Chang, Min-Hung Lee, Hsiao Hsuan Hsu, Shiang Shiou Yen

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    36 Citations (Scopus)

    Abstract

    In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10-15 A/μm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔVT window of 2.8V, fast 20-ns speed, 103s retention at 85°C, and long extrapolated 1016 endurance at 85°C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.

    Original languageEnglish
    Title of host publication2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    PagesT184-T185
    ISBN (Electronic)9784863485013
    DOIs
    Publication statusPublished - 2015 Aug 25
    EventSymposium on VLSI Technology, VLSI Technology 2015 - Kyoto, Japan
    Duration: 2015 Jun 162015 Jun 18

    Publication series

    NameDigest of Technical Papers - Symposium on VLSI Technology
    Volume2015-August
    ISSN (Print)0743-1562

    Other

    OtherSymposium on VLSI Technology, VLSI Technology 2015
    Country/TerritoryJapan
    CityKyoto
    Period2015/06/162015/06/18

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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