Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High-k Metal Gate CMOS Process

Chun Yu Lin, Yi Han Wu, Ming Dou Ker

Research output: Contribution to journalArticlepeer-review

26 Citations (Scopus)


To effectively protect integrated circuits from electrostatic discharge (ESD) damage, this letter proposes a silicon-controlled rectifier (SCR) device with low trigger voltage, low leakage current, low parasitic capacitance, and which requires no additional process step. The proposed device uses two metal gates to separate the anode and cathode of the SCR to reduce the leakage current. These two gates are well controlled to trigger the SCR device. The test devices have been implemented and verified in a 28-nm high-k metal gate CMOS process. Experimental results show that the proposed SCR exhibits a low trigger voltage (<;3 V), low leakage current (<;5 nA), low parasitic capacitance (<; 40 fF), and sufficient ESD robustness (> 1 kV in human-body-model tests). Based on its good performances during ESD stress and normal circuit operating conditions, the proposed SCR device is very suitable for ESD protection in advanced CMOS processes.

Original languageEnglish
Pages (from-to)1387-1390
Number of pages4
JournalIEEE Electron Device Letters
Issue number11
Publication statusPublished - 2016 Nov


  • Electrostatic discharge (ESD)
  • leakage current
  • parasitic capacitance
  • silicon-controlled rectifier (SCR)
  • trigger voltage

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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