Low-capaeitance SCR with waffle layout structure for on-chip ESD protection in RF ICs

Chun Yu Lin, Ming Dou Ker

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

Silicon-controlled rectifier (SCR) has been used as an effective on-chip ESD protection device in CMOS technology due to the highest ESD robustness. In this work, the waffle layout structure for SCR can achieve smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to ESD protection device can be reduced. The proposed waffle SCR with low parasitic capacitance is suitable for on-chip ESD protection in RF ICs.

Original languageEnglish
Title of host publicationProceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007
Pages749-752
Number of pages4
DOIs
Publication statusPublished - 2007 Oct 2
Event2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007 - Honolulu, HI, United States
Duration: 2007 Jun 32007 Jun 5

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517

Other

Other2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007
CountryUnited States
CityHonolulu, HI
Period07/6/307/6/5

Fingerprint

Thyristors
Capacitance
Degradation
Networks (circuits)

Keywords

  • Electrostatic discharges (ESD)
  • Radio-frequency integrated circuit (RF IC)
  • Silicon-controlled rectifier (SCR)

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Lin, C. Y., & Ker, M. D. (2007). Low-capaeitance SCR with waffle layout structure for on-chip ESD protection in RF ICs. In Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007 (pp. 749-752). [4266539] (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). https://doi.org/10.1109/RFIC.2007.380991

Low-capaeitance SCR with waffle layout structure for on-chip ESD protection in RF ICs. / Lin, Chun Yu; Ker, Ming Dou.

Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007. 2007. p. 749-752 4266539 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lin, CY & Ker, MD 2007, Low-capaeitance SCR with waffle layout structure for on-chip ESD protection in RF ICs. in Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007., 4266539, Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, pp. 749-752, 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007, Honolulu, HI, United States, 07/6/3. https://doi.org/10.1109/RFIC.2007.380991
Lin CY, Ker MD. Low-capaeitance SCR with waffle layout structure for on-chip ESD protection in RF ICs. In Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007. 2007. p. 749-752. 4266539. (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). https://doi.org/10.1109/RFIC.2007.380991
Lin, Chun Yu ; Ker, Ming Dou. / Low-capaeitance SCR with waffle layout structure for on-chip ESD protection in RF ICs. Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007. 2007. pp. 749-752 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).
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