TY - JOUR
T1 - Low-C ESD protection design with dual resistor-triggered SCRs in CMOS technology
AU - Lin, Chun Yu
AU - Chen, Chun Yu
N1 - Funding Information:
ACKNOWLEDGMENT The authors would like to thank National Chip Implementation Center (CIC), Taiwan, for the support of chip fabrication, and Hanwa Electronic Ind. Co., Ltd., Japan, for setting up the ESD tester. The authors would also like to thank Prof. Ming-Dou Ker and his research group in National Chiao Tung University, Taiwan, for their great help during measurement.
Funding Information:
Manuscript received February 22, 2018; accepted March 15, 2018. Date of publication March 20, 2018; date of current version June 5, 2018. This work was supported in part by the Ministry of Science and Technology (MOST), Taiwan, under Contract MOST 107-2622-E-003-001-CC2 and Contract MOST 106-2221-E-003-033, and in part by Amazing Microelectronic Corporation, Taiwan. (Corresponding author: Chun-Yu Lin.) The authors are with the Department of Electrical Engineering, National Taiwan Normal University, Taipei 106, Taiwan (e-mail: cy.lin@ieee.org).
Publisher Copyright:
© 2001-2011 IEEE.
PY - 2018/6
Y1 - 2018/6
N2 - The electrostatic discharge (ESD) protection design with low parasitic capacitance seen at I/O pad is needed for high-frequency applications. Conventional ESD protection designs with dual diodes or dual stacked diodes have been used for gigahertz applications. To further reduce the parasitic capacitance, the ESD protection design by using complementary resistor-triggered silicon-controlled rectifiers (RTSCRs) is proposed in this paper. The proposed design includes a P-type RTSCR between I/O and VDD, an N-type RTSCR between I/O and VSS, and a power clamp circuit between VDD and VSS to achieve whole-chip ESD protection. Verified in silicon chip, the RTSCRs have the advantages, such as the sufficient low clamping voltage and lower parasitic capacitance, as compared with the conventional ESD protection designs. Therefore, the proposed design is suitable for low-C ESD protection in CMOS technology.
AB - The electrostatic discharge (ESD) protection design with low parasitic capacitance seen at I/O pad is needed for high-frequency applications. Conventional ESD protection designs with dual diodes or dual stacked diodes have been used for gigahertz applications. To further reduce the parasitic capacitance, the ESD protection design by using complementary resistor-triggered silicon-controlled rectifiers (RTSCRs) is proposed in this paper. The proposed design includes a P-type RTSCR between I/O and VDD, an N-type RTSCR between I/O and VSS, and a power clamp circuit between VDD and VSS to achieve whole-chip ESD protection. Verified in silicon chip, the RTSCRs have the advantages, such as the sufficient low clamping voltage and lower parasitic capacitance, as compared with the conventional ESD protection designs. Therefore, the proposed design is suitable for low-C ESD protection in CMOS technology.
KW - Electrostatic discharge (ESD)
KW - low capacitance
KW - silicon-controlled rectifier (SCR)
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U2 - 10.1109/TDMR.2018.2817389
DO - 10.1109/TDMR.2018.2817389
M3 - Article
AN - SCOPUS:85044269294
SN - 1530-4388
VL - 18
SP - 197
EP - 204
JO - IEEE Transactions on Device and Materials Reliability
JF - IEEE Transactions on Device and Materials Reliability
IS - 2
ER -