Low-C ESD protection design with dual resistor-triggered SCRs in CMOS technology

Chun Yu Lin*, Chun Yu Chen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)


The electrostatic discharge (ESD) protection design with low parasitic capacitance seen at I/O pad is needed for high-frequency applications. Conventional ESD protection designs with dual diodes or dual stacked diodes have been used for gigahertz applications. To further reduce the parasitic capacitance, the ESD protection design by using complementary resistor-triggered silicon-controlled rectifiers (RTSCRs) is proposed in this paper. The proposed design includes a P-type RTSCR between I/O and VDD, an N-type RTSCR between I/O and VSS, and a power clamp circuit between VDD and VSS to achieve whole-chip ESD protection. Verified in silicon chip, the RTSCRs have the advantages, such as the sufficient low clamping voltage and lower parasitic capacitance, as compared with the conventional ESD protection designs. Therefore, the proposed design is suitable for low-C ESD protection in CMOS technology.

Original languageEnglish
Pages (from-to)197-204
Number of pages8
JournalIEEE Transactions on Device and Materials Reliability
Issue number2
Publication statusPublished - 2018 Jun


  • Electrostatic discharge (ESD)
  • low capacitance
  • silicon-controlled rectifier (SCR)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering


Dive into the research topics of 'Low-C ESD protection design with dual resistor-triggered SCRs in CMOS technology'. Together they form a unique fingerprint.

Cite this