Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process

Ming Dou Ker; Chun-Yu Lin; Tang Long Chang

doi:10.1109/VDAT.2011.5783551

Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process

Ming Dou Ker, Chun-Yu Lin, Tang Long Chang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.

Original language	English
Title of host publication	Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Pages	374-377
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2011.5783551
Publication status	Published - 2011 Jun 28
Event	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan Duration: 2011 Apr 25 → 2011 Apr 28

Other

Other	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Country	Taiwan
City	Hsinchu
Period	2011/04/25 → 2011/04/28

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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Ker, MD, Lin, C-Y & Chang, TL 2011, Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process. in Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011., 5783551, pp. 374-377, 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, Hsinchu, Taiwan, 2011/04/25. https://doi.org/10.1109/VDAT.2011.5783551

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abstract = "Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.",

author = "Ker, {Ming Dou} and Chun-Yu Lin and Chang, {Tang Long}",

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doi = "10.1109/VDAT.2011.5783551",

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booktitle = "Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011",

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N2 - Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.

AB - Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.

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Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process

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