Abstract
Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 |
| Pages | 374-377 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2011 Jun 28 |
| Event | 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan Duration: 2011 Apr 25 → 2011 Apr 28 |
Other
| Other | 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 |
|---|---|
| Country | Taiwan |
| City | Hsinchu |
| Period | 11/4/25 → 11/4/28 |
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ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process. / Ker, Ming Dou; Lin, Chun-Yu; Chang, Tang Long.
Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 374-377 5783551.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process
AU - Ker, Ming Dou
AU - Lin, Chun-Yu
AU - Chang, Tang Long
PY - 2011/6/28
Y1 - 2011/6/28
N2 - Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.
AB - Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.
UR - http://www.scopus.com/inward/record.url?scp=79959503673&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79959503673&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2011.5783551
DO - 10.1109/VDAT.2011.5783551
M3 - Conference contribution
AN - SCOPUS:79959503673
SN - 9781424484997
SP - 374
EP - 377
BT - Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
ER -