TY - GEN
T1 - K-band low-noise amplifier with stacked-diode esd protection in nanoscale CMOS technology
AU - Lin, Meng Ting
AU - Lin, Chun Yu
N1 - Funding Information:
This work was supported in part by Ministry of Science and Technology (MOST), Taiwan, under Contract of MOST 106-2622-E-003-001-CC2, and in part by Amazing Microelectronic Corp., Taiwan. The authors would like to thank National Chip Implementation Center (CIC), Taiwan, for the support of chip fabrication. The authors would also like to thank Prof. Ming-Dou Ker, Mr. Jie-Ting Chen, and Mr. Rong-Kun Chang in National Chiao Tung University, Taiwan, for their great help during ESD testing.
Publisher Copyright:
© 2017 IEEE.
PY - 2017/10/5
Y1 - 2017/10/5
N2 - An electrostatic discharge (ESD) protection design by using stacked diodes and silicon-controlled rectifier (SCR) as power clamp is presented to protect a K-band low-noise-amplifier in nanoscale CMOS process. Experimental results show that the proposed design can achieve higher ESD robustness without degrading the radio-frequency (RF) performance. Based on its good performances during ESD stress and RF circuit operating conditions, the proposed design is very suitable for RF ESD protection.
AB - An electrostatic discharge (ESD) protection design by using stacked diodes and silicon-controlled rectifier (SCR) as power clamp is presented to protect a K-band low-noise-amplifier in nanoscale CMOS process. Experimental results show that the proposed design can achieve higher ESD robustness without degrading the radio-frequency (RF) performance. Based on its good performances during ESD stress and RF circuit operating conditions, the proposed design is very suitable for RF ESD protection.
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U2 - 10.1109/IPFA.2017.8060074
DO - 10.1109/IPFA.2017.8060074
M3 - Conference contribution
AN - SCOPUS:85045069905
T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
SP - 1
EP - 4
BT - 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
Y2 - 4 July 2017 through 7 July 2017
ER -