Among three chip-level electrostatic discharge (ESD) test standards, which were human-body model (HBM), machine model (MM), and charged-device model (CDM), the CDM ESD events became critical due to the larger and faster discharging currents. Besides input/output (I/O) circuits which were connected to I/O pads, core circuits also suffered from CDM ESD events caused by coupled currents between I/O lines and core lines. In this work, the CDM ESD robustness of the core circuits with and without inserting shielding lines were investigated in a 65-nm CMOS process. Verified in a silicon chip, the CDM ESD robustness of the core circuits with shielding lines were degraded. The failure mechanism of the test circuits was also investigated in this work.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Safety, Risk, Reliability and Quality
- Condensed Matter Physics
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering