Investigation of consequent process-induced stress for N-type metal oxide semiconductor field effect transistor with a sunken shallow trench isolation pattern

Chang Chun Lee, Chuan-Hsi Liu, Rong Hao Deng, Hung Wen Hsu, Kuo Ning Chiang

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

The adoption of shallow trench isolation (STI) integrated with a contact etching stop layer (CESL) is regarded as an important technique in strain engineering that significantly boosts transistor mobility of nanoscale devices because the node technology of the metal-oxide-semiconductor field-effect transistor (MOSFET) is continually scaled down to 22 nm and lower. A finite element method based on stress simulation is implemented in this research to investigate the effects of STI geometric profiles on n-type MOSFET performance. The mechanism for transferring STI and CESL intrinsic stresses under the aforementioned conditions to the silicon (Si) channel is explained by considering the major procedures of process-induced stress. Results indicate that the approaches of suitable sunken STI patterns are more useful than those of a flat STI prototype because a difference in the resultant stress distribution for the Si channel region is introduced by the device profiles. The piezoresistance effect of Si is being actively explored at present to improve the characteristic of transistors because this effect has been extensively used in mechanical stress technology. A crystal strain resulting in a change in electrical conductivity is observed because of the aforementioned piezoresistance effect. Induced mobility gains from STI and CESL stressors are systematically observed. Integrating a tensile CESL and an STI stressor region results in almost 10% to 20% enhancement in carrier mobility.

Original languageEnglish
Pages (from-to)323-328
Number of pages6
JournalThin Solid Films
Volume557
DOIs
Publication statusPublished - 2014 Apr 30

Fingerprint

MOSFET devices
metal oxide semiconductors
Etching
isolation
Silicon
field effect transistors
etching
Transistors
Carrier mobility
silicon
transistors
Stress concentration
n-type semiconductors
Finite element method
Crystals
profiles
carrier mobility
acceleration (physics)
stress distribution
finite element method

Keywords

  • Contact etching stop layer (CESL)
  • Finite element analysis (FEA)
  • MOSFET
  • Piezoresistance effect
  • Shallow trench isolation (STI)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Surfaces and Interfaces
  • Surfaces, Coatings and Films
  • Metals and Alloys
  • Materials Chemistry

Cite this

Investigation of consequent process-induced stress for N-type metal oxide semiconductor field effect transistor with a sunken shallow trench isolation pattern. / Lee, Chang Chun; Liu, Chuan-Hsi; Deng, Rong Hao; Hsu, Hung Wen; Chiang, Kuo Ning.

In: Thin Solid Films, Vol. 557, 30.04.2014, p. 323-328.

Research output: Contribution to journalArticle

@article{3501b94bb5d449858fb8455bceaa03d3,
title = "Investigation of consequent process-induced stress for N-type metal oxide semiconductor field effect transistor with a sunken shallow trench isolation pattern",
abstract = "The adoption of shallow trench isolation (STI) integrated with a contact etching stop layer (CESL) is regarded as an important technique in strain engineering that significantly boosts transistor mobility of nanoscale devices because the node technology of the metal-oxide-semiconductor field-effect transistor (MOSFET) is continually scaled down to 22 nm and lower. A finite element method based on stress simulation is implemented in this research to investigate the effects of STI geometric profiles on n-type MOSFET performance. The mechanism for transferring STI and CESL intrinsic stresses under the aforementioned conditions to the silicon (Si) channel is explained by considering the major procedures of process-induced stress. Results indicate that the approaches of suitable sunken STI patterns are more useful than those of a flat STI prototype because a difference in the resultant stress distribution for the Si channel region is introduced by the device profiles. The piezoresistance effect of Si is being actively explored at present to improve the characteristic of transistors because this effect has been extensively used in mechanical stress technology. A crystal strain resulting in a change in electrical conductivity is observed because of the aforementioned piezoresistance effect. Induced mobility gains from STI and CESL stressors are systematically observed. Integrating a tensile CESL and an STI stressor region results in almost 10{\%} to 20{\%} enhancement in carrier mobility.",
keywords = "Contact etching stop layer (CESL), Finite element analysis (FEA), MOSFET, Piezoresistance effect, Shallow trench isolation (STI)",
author = "Lee, {Chang Chun} and Chuan-Hsi Liu and Deng, {Rong Hao} and Hsu, {Hung Wen} and Chiang, {Kuo Ning}",
year = "2014",
month = "4",
day = "30",
doi = "10.1016/j.tsf.2013.10.027",
language = "English",
volume = "557",
pages = "323--328",
journal = "Thin Solid Films",
issn = "0040-6090",
publisher = "Elsevier",

}

TY - JOUR

T1 - Investigation of consequent process-induced stress for N-type metal oxide semiconductor field effect transistor with a sunken shallow trench isolation pattern

AU - Lee, Chang Chun

AU - Liu, Chuan-Hsi

AU - Deng, Rong Hao

AU - Hsu, Hung Wen

AU - Chiang, Kuo Ning

PY - 2014/4/30

Y1 - 2014/4/30

N2 - The adoption of shallow trench isolation (STI) integrated with a contact etching stop layer (CESL) is regarded as an important technique in strain engineering that significantly boosts transistor mobility of nanoscale devices because the node technology of the metal-oxide-semiconductor field-effect transistor (MOSFET) is continually scaled down to 22 nm and lower. A finite element method based on stress simulation is implemented in this research to investigate the effects of STI geometric profiles on n-type MOSFET performance. The mechanism for transferring STI and CESL intrinsic stresses under the aforementioned conditions to the silicon (Si) channel is explained by considering the major procedures of process-induced stress. Results indicate that the approaches of suitable sunken STI patterns are more useful than those of a flat STI prototype because a difference in the resultant stress distribution for the Si channel region is introduced by the device profiles. The piezoresistance effect of Si is being actively explored at present to improve the characteristic of transistors because this effect has been extensively used in mechanical stress technology. A crystal strain resulting in a change in electrical conductivity is observed because of the aforementioned piezoresistance effect. Induced mobility gains from STI and CESL stressors are systematically observed. Integrating a tensile CESL and an STI stressor region results in almost 10% to 20% enhancement in carrier mobility.

AB - The adoption of shallow trench isolation (STI) integrated with a contact etching stop layer (CESL) is regarded as an important technique in strain engineering that significantly boosts transistor mobility of nanoscale devices because the node technology of the metal-oxide-semiconductor field-effect transistor (MOSFET) is continually scaled down to 22 nm and lower. A finite element method based on stress simulation is implemented in this research to investigate the effects of STI geometric profiles on n-type MOSFET performance. The mechanism for transferring STI and CESL intrinsic stresses under the aforementioned conditions to the silicon (Si) channel is explained by considering the major procedures of process-induced stress. Results indicate that the approaches of suitable sunken STI patterns are more useful than those of a flat STI prototype because a difference in the resultant stress distribution for the Si channel region is introduced by the device profiles. The piezoresistance effect of Si is being actively explored at present to improve the characteristic of transistors because this effect has been extensively used in mechanical stress technology. A crystal strain resulting in a change in electrical conductivity is observed because of the aforementioned piezoresistance effect. Induced mobility gains from STI and CESL stressors are systematically observed. Integrating a tensile CESL and an STI stressor region results in almost 10% to 20% enhancement in carrier mobility.

KW - Contact etching stop layer (CESL)

KW - Finite element analysis (FEA)

KW - MOSFET

KW - Piezoresistance effect

KW - Shallow trench isolation (STI)

UR - http://www.scopus.com/inward/record.url?scp=84897917826&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84897917826&partnerID=8YFLogxK

U2 - 10.1016/j.tsf.2013.10.027

DO - 10.1016/j.tsf.2013.10.027

M3 - Article

AN - SCOPUS:84897917826

VL - 557

SP - 323

EP - 328

JO - Thin Solid Films

JF - Thin Solid Films

SN - 0040-6090

ER -