Interfacial-Layer-Free Ge0.95Si0.05Nanosheet FeFETs

Wan Hsuan Hsieh; Yu Rui Chen; Yi Chun Liu; Zefu Zhao; Jia Yang Lee; Chien Te Tu; Bo Wei Huang; Jer Fu Wang; M. H. Lee; C. W. Liu

doi:10.1109/TED.2024.3356444

Interfacial-Layer-Free Ge_0.95Si_0.05Nanosheet FeFETs

Wan Hsuan Hsieh
, Yu Rui Chen
, Yi Chun Liu
, Zefu Zhao
, Jia Yang Lee
, Chien Te Tu
, Bo Wei Huang
, Jer Fu Wang
, M. H. Lee
, C. W. Liu^*

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

The substantial memory window (MW) of 1.8 V is achieved by utilizing stacked two nanosheet (NS) gate-all-around (GAA) Ge0.95 Si0.05 ferroelectric field-effect transistors (FeFETs), employing a low write voltage of 2 V. The channel phosphorus concentration 1E18 cm-3 is used to erase the absence of interfacial layer (IL) can reduce the operation voltage. An isotropic wet etching process is employed for channel release. The stacked two NSs offer the advantages of reducing cell-to-cell variation and doubling the read current. Additionally, the stability of data storage is demonstrated with the data retention of >1E4 s, linearly extrapolated to a span of 10 years, and exhibiting high endurance >1E11 cycles. The thermal budget is as low as 400 °C.

Original language	English
Pages (from-to)	1758-1763
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	71
Issue number	3
DOIs	https://doi.org/10.1109/TED.2024.3356444
Publication status	Published - 2024 Mar 1
Externally published	Yes

Keywords

Chemical vapor deposition
GeSi
ferroelectric field-effect transistor (FeFET)
gate-all-around (GAA)
interfacial layer
isotropic wet etching
nanosheets (NSs)

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/TED.2024.3356444

Cite this

@article{1314389d78b3437bb24119cebc5e8b61,

title = "Interfacial-Layer-Free Ge0.95Si0.05Nanosheet FeFETs",

abstract = "The substantial memory window (MW) of 1.8 V is achieved by utilizing stacked two nanosheet (NS) gate-all-around (GAA) Ge0.95 Si0.05 ferroelectric field-effect transistors (FeFETs), employing a low write voltage of 2 V. The channel phosphorus concentration 1E18 cm-3 is used to erase the absence of interfacial layer (IL) can reduce the operation voltage. An isotropic wet etching process is employed for channel release. The stacked two NSs offer the advantages of reducing cell-to-cell variation and doubling the read current. Additionally, the stability of data storage is demonstrated with the data retention of >1E4 s, linearly extrapolated to a span of 10 years, and exhibiting high endurance >1E11 cycles. The thermal budget is as low as 400 °C.",

keywords = "Chemical vapor deposition, GeSi, ferroelectric field-effect transistor (FeFET), gate-all-around (GAA), interfacial layer, isotropic wet etching, nanosheets (NSs)",

author = "Hsieh, \{Wan Hsuan\} and Chen, \{Yu Rui\} and Liu, \{Yi Chun\} and Zefu Zhao and Lee, \{Jia Yang\} and Tu, \{Chien Te\} and Huang, \{Bo Wei\} and Wang, \{Jer Fu\} and Lee, \{M. H.\} and Liu, \{C. W.\}",

note = "Publisher Copyright: {\textcopyright} 1963-2012 IEEE.",

year = "2024",

month = mar,

day = "1",

doi = "10.1109/TED.2024.3356444",

language = "English",

volume = "71",

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TY - JOUR

T1 - Interfacial-Layer-Free Ge0.95Si0.05Nanosheet FeFETs

AU - Hsieh, Wan Hsuan

AU - Chen, Yu Rui

AU - Liu, Yi Chun

AU - Zhao, Zefu

AU - Lee, Jia Yang

AU - Tu, Chien Te

AU - Huang, Bo Wei

AU - Wang, Jer Fu

AU - Lee, M. H.

AU - Liu, C. W.

PY - 2024/3/1

Y1 - 2024/3/1

N2 - The substantial memory window (MW) of 1.8 V is achieved by utilizing stacked two nanosheet (NS) gate-all-around (GAA) Ge0.95 Si0.05 ferroelectric field-effect transistors (FeFETs), employing a low write voltage of 2 V. The channel phosphorus concentration 1E18 cm-3 is used to erase the absence of interfacial layer (IL) can reduce the operation voltage. An isotropic wet etching process is employed for channel release. The stacked two NSs offer the advantages of reducing cell-to-cell variation and doubling the read current. Additionally, the stability of data storage is demonstrated with the data retention of >1E4 s, linearly extrapolated to a span of 10 years, and exhibiting high endurance >1E11 cycles. The thermal budget is as low as 400 °C.

AB - The substantial memory window (MW) of 1.8 V is achieved by utilizing stacked two nanosheet (NS) gate-all-around (GAA) Ge0.95 Si0.05 ferroelectric field-effect transistors (FeFETs), employing a low write voltage of 2 V. The channel phosphorus concentration 1E18 cm-3 is used to erase the absence of interfacial layer (IL) can reduce the operation voltage. An isotropic wet etching process is employed for channel release. The stacked two NSs offer the advantages of reducing cell-to-cell variation and doubling the read current. Additionally, the stability of data storage is demonstrated with the data retention of >1E4 s, linearly extrapolated to a span of 10 years, and exhibiting high endurance >1E11 cycles. The thermal budget is as low as 400 °C.

KW - Chemical vapor deposition

KW - GeSi

KW - ferroelectric field-effect transistor (FeFET)

KW - gate-all-around (GAA)

KW - interfacial layer

KW - isotropic wet etching

KW - nanosheets (NSs)

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DO - 10.1109/TED.2024.3356444

M3 - Article

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VL - 71

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JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

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