Interaction influence of S/D GeSi lattice mismatch and stress gradient of CESL on nano-scaled strained nMOSFETs

Chang Chun Lee, Yen Ting Kuo, Chuan Hsi Liu

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

The intrinsic stress of thin films has become an important resource as advanced strain engineering is introduced into nanoscaled semiconductor devices. The performance of preferred device infrastructure can be studied by estimating stress-induced mobility gain. However, traditional simulation approaches for device stress typically do not consider the eventual consequence of the stress gradient of strained thin films on nanoscaled transistor stress prediction. Thus, the actual operating characteristic of concerned devices can be easily misunderstood. To resolve this issue, this research presents a fabrication-oriented simulation methodology for device stress and combines it with a multi-layered deposition model for thin film. This study aims to explore stress-induced effects on the performance of a Ge-based testing vehicle for 20 nm n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) with Ge1−xSix alloys embedded into the source/drain regions of the device. Intrinsic stress is introduced via a 1.0 GPa tensile contact etch stop layer (CESL). Analysis results indicate that stress contours adjacent to the top of the device gate are different from those obtained using the conventional simulation method. Moreover, greater CESL stress passes through the spacer and reaches the device channel. Furthermore, a relationship between the stress components and piezoresistivity coefficients of the Ge material is adopted to estimate the width dependence of the Ge-based nMOSFET on its mobility gain. A maximum mobility gain of up to 60.87% is acquired from the estimated results, and a channel width of 200 nm is preserved.

Original languageEnglish
Pages (from-to)254-259
Number of pages6
JournalMaterials Science in Semiconductor Processing
Volume70
DOIs
Publication statusPublished - 2017 Nov 1

Fingerprint

Lattice mismatch
n-type semiconductors
MOSFET devices
metal oxide semiconductors
field effect transistors
gradients
interactions
Thin films
thin films
simulation
semiconductor devices
Semiconductor devices
spacers
resources
vehicles
estimating
transistors
Transistors
engineering
methodology

Keywords

  • CESL
  • Device stress simulation
  • GeSi alloy
  • Strained engineering
  • Stress gradient

ASJC Scopus subject areas

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

Cite this

Interaction influence of S/D GeSi lattice mismatch and stress gradient of CESL on nano-scaled strained nMOSFETs. / Lee, Chang Chun; Kuo, Yen Ting; Liu, Chuan Hsi.

In: Materials Science in Semiconductor Processing, Vol. 70, 01.11.2017, p. 254-259.

Research output: Contribution to journalArticle

@article{a884c62513b6432894d7dc2d900175fe,
title = "Interaction influence of S/D GeSi lattice mismatch and stress gradient of CESL on nano-scaled strained nMOSFETs",
abstract = "The intrinsic stress of thin films has become an important resource as advanced strain engineering is introduced into nanoscaled semiconductor devices. The performance of preferred device infrastructure can be studied by estimating stress-induced mobility gain. However, traditional simulation approaches for device stress typically do not consider the eventual consequence of the stress gradient of strained thin films on nanoscaled transistor stress prediction. Thus, the actual operating characteristic of concerned devices can be easily misunderstood. To resolve this issue, this research presents a fabrication-oriented simulation methodology for device stress and combines it with a multi-layered deposition model for thin film. This study aims to explore stress-induced effects on the performance of a Ge-based testing vehicle for 20 nm n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) with Ge1−xSix alloys embedded into the source/drain regions of the device. Intrinsic stress is introduced via a 1.0 GPa tensile contact etch stop layer (CESL). Analysis results indicate that stress contours adjacent to the top of the device gate are different from those obtained using the conventional simulation method. Moreover, greater CESL stress passes through the spacer and reaches the device channel. Furthermore, a relationship between the stress components and piezoresistivity coefficients of the Ge material is adopted to estimate the width dependence of the Ge-based nMOSFET on its mobility gain. A maximum mobility gain of up to 60.87{\%} is acquired from the estimated results, and a channel width of 200 nm is preserved.",
keywords = "CESL, Device stress simulation, GeSi alloy, Strained engineering, Stress gradient",
author = "Lee, {Chang Chun} and Kuo, {Yen Ting} and Liu, {Chuan Hsi}",
year = "2017",
month = "11",
day = "1",
doi = "10.1016/j.mssp.2016.12.037",
language = "English",
volume = "70",
pages = "254--259",
journal = "Materials Science in Semiconductor Processing",
issn = "1369-8001",
publisher = "Elsevier Limited",

}

TY - JOUR

T1 - Interaction influence of S/D GeSi lattice mismatch and stress gradient of CESL on nano-scaled strained nMOSFETs

AU - Lee, Chang Chun

AU - Kuo, Yen Ting

AU - Liu, Chuan Hsi

PY - 2017/11/1

Y1 - 2017/11/1

N2 - The intrinsic stress of thin films has become an important resource as advanced strain engineering is introduced into nanoscaled semiconductor devices. The performance of preferred device infrastructure can be studied by estimating stress-induced mobility gain. However, traditional simulation approaches for device stress typically do not consider the eventual consequence of the stress gradient of strained thin films on nanoscaled transistor stress prediction. Thus, the actual operating characteristic of concerned devices can be easily misunderstood. To resolve this issue, this research presents a fabrication-oriented simulation methodology for device stress and combines it with a multi-layered deposition model for thin film. This study aims to explore stress-induced effects on the performance of a Ge-based testing vehicle for 20 nm n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) with Ge1−xSix alloys embedded into the source/drain regions of the device. Intrinsic stress is introduced via a 1.0 GPa tensile contact etch stop layer (CESL). Analysis results indicate that stress contours adjacent to the top of the device gate are different from those obtained using the conventional simulation method. Moreover, greater CESL stress passes through the spacer and reaches the device channel. Furthermore, a relationship between the stress components and piezoresistivity coefficients of the Ge material is adopted to estimate the width dependence of the Ge-based nMOSFET on its mobility gain. A maximum mobility gain of up to 60.87% is acquired from the estimated results, and a channel width of 200 nm is preserved.

AB - The intrinsic stress of thin films has become an important resource as advanced strain engineering is introduced into nanoscaled semiconductor devices. The performance of preferred device infrastructure can be studied by estimating stress-induced mobility gain. However, traditional simulation approaches for device stress typically do not consider the eventual consequence of the stress gradient of strained thin films on nanoscaled transistor stress prediction. Thus, the actual operating characteristic of concerned devices can be easily misunderstood. To resolve this issue, this research presents a fabrication-oriented simulation methodology for device stress and combines it with a multi-layered deposition model for thin film. This study aims to explore stress-induced effects on the performance of a Ge-based testing vehicle for 20 nm n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) with Ge1−xSix alloys embedded into the source/drain regions of the device. Intrinsic stress is introduced via a 1.0 GPa tensile contact etch stop layer (CESL). Analysis results indicate that stress contours adjacent to the top of the device gate are different from those obtained using the conventional simulation method. Moreover, greater CESL stress passes through the spacer and reaches the device channel. Furthermore, a relationship between the stress components and piezoresistivity coefficients of the Ge material is adopted to estimate the width dependence of the Ge-based nMOSFET on its mobility gain. A maximum mobility gain of up to 60.87% is acquired from the estimated results, and a channel width of 200 nm is preserved.

KW - CESL

KW - Device stress simulation

KW - GeSi alloy

KW - Strained engineering

KW - Stress gradient

UR - http://www.scopus.com/inward/record.url?scp=85008426033&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85008426033&partnerID=8YFLogxK

U2 - 10.1016/j.mssp.2016.12.037

DO - 10.1016/j.mssp.2016.12.037

M3 - Article

AN - SCOPUS:85008426033

VL - 70

SP - 254

EP - 259

JO - Materials Science in Semiconductor Processing

JF - Materials Science in Semiconductor Processing

SN - 1369-8001

ER -