Intelligent random vector generator based on probability analysis of circuit structure

Yu Min Kuo, Cheng Hung Lin, Chun Yao Wang, Shih Chieh Chang, Pei Hsin Ho

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Design verification has become a bottleneck of modern designs. Recently, simulation-based random verification has attracted a lot of interests due to its effectiveness in uncovering obscure bugs. Designers are often required to provide the input probabilities while conducting the random verification. However, it is extremely difficult for designers to provide accurate input probabilities. In this paper, we propose an iterative algorithm that derives good input probabilities so that the design intent can be exercised effectively for functional verification. We conduct extensive experiments on both benchmark circuit and industrial designs. The experimental results are very promising.

Original languageEnglish
Title of host publicationProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007
Pages344-349
Number of pages6
DOIs
Publication statusPublished - 2007 Aug 28
Event8th International Symposium on Quality Electronic Design, ISQED 2007 - San Jose, CA, United States
Duration: 2007 Mar 262007 Mar 28

Publication series

NameProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

Other

Other8th International Symposium on Quality Electronic Design, ISQED 2007
CountryUnited States
CitySan Jose, CA
Period07/3/2607/3/28

Fingerprint

Networks (circuits)
Product design
Experiments

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Kuo, Y. M., Lin, C. H., Wang, C. Y., Chang, S. C., & Ho, P. H. (2007). Intelligent random vector generator based on probability analysis of circuit structure. In Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007 (pp. 344-349). [4149059] (Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007). https://doi.org/10.1109/ISQED.2007.91

Intelligent random vector generator based on probability analysis of circuit structure. / Kuo, Yu Min; Lin, Cheng Hung; Wang, Chun Yao; Chang, Shih Chieh; Ho, Pei Hsin.

Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007. 2007. p. 344-349 4149059 (Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kuo, YM, Lin, CH, Wang, CY, Chang, SC & Ho, PH 2007, Intelligent random vector generator based on probability analysis of circuit structure. in Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007., 4149059, Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007, pp. 344-349, 8th International Symposium on Quality Electronic Design, ISQED 2007, San Jose, CA, United States, 07/3/26. https://doi.org/10.1109/ISQED.2007.91
Kuo YM, Lin CH, Wang CY, Chang SC, Ho PH. Intelligent random vector generator based on probability analysis of circuit structure. In Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007. 2007. p. 344-349. 4149059. (Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007). https://doi.org/10.1109/ISQED.2007.91
Kuo, Yu Min ; Lin, Cheng Hung ; Wang, Chun Yao ; Chang, Shih Chieh ; Ho, Pei Hsin. / Intelligent random vector generator based on probability analysis of circuit structure. Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007. 2007. pp. 344-349 (Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007).
@inproceedings{0fb59b2563e64edba93bf5f974793092,
title = "Intelligent random vector generator based on probability analysis of circuit structure",
abstract = "Design verification has become a bottleneck of modern designs. Recently, simulation-based random verification has attracted a lot of interests due to its effectiveness in uncovering obscure bugs. Designers are often required to provide the input probabilities while conducting the random verification. However, it is extremely difficult for designers to provide accurate input probabilities. In this paper, we propose an iterative algorithm that derives good input probabilities so that the design intent can be exercised effectively for functional verification. We conduct extensive experiments on both benchmark circuit and industrial designs. The experimental results are very promising.",
author = "Kuo, {Yu Min} and Lin, {Cheng Hung} and Wang, {Chun Yao} and Chang, {Shih Chieh} and Ho, {Pei Hsin}",
year = "2007",
month = "8",
day = "28",
doi = "10.1109/ISQED.2007.91",
language = "English",
isbn = "0769527957",
series = "Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007",
pages = "344--349",
booktitle = "Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007",

}

TY - GEN

T1 - Intelligent random vector generator based on probability analysis of circuit structure

AU - Kuo, Yu Min

AU - Lin, Cheng Hung

AU - Wang, Chun Yao

AU - Chang, Shih Chieh

AU - Ho, Pei Hsin

PY - 2007/8/28

Y1 - 2007/8/28

N2 - Design verification has become a bottleneck of modern designs. Recently, simulation-based random verification has attracted a lot of interests due to its effectiveness in uncovering obscure bugs. Designers are often required to provide the input probabilities while conducting the random verification. However, it is extremely difficult for designers to provide accurate input probabilities. In this paper, we propose an iterative algorithm that derives good input probabilities so that the design intent can be exercised effectively for functional verification. We conduct extensive experiments on both benchmark circuit and industrial designs. The experimental results are very promising.

AB - Design verification has become a bottleneck of modern designs. Recently, simulation-based random verification has attracted a lot of interests due to its effectiveness in uncovering obscure bugs. Designers are often required to provide the input probabilities while conducting the random verification. However, it is extremely difficult for designers to provide accurate input probabilities. In this paper, we propose an iterative algorithm that derives good input probabilities so that the design intent can be exercised effectively for functional verification. We conduct extensive experiments on both benchmark circuit and industrial designs. The experimental results are very promising.

UR - http://www.scopus.com/inward/record.url?scp=34548128221&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34548128221&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2007.91

DO - 10.1109/ISQED.2007.91

M3 - Conference contribution

AN - SCOPUS:34548128221

SN - 0769527957

SN - 9780769527956

T3 - Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

SP - 344

EP - 349

BT - Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

ER -