Improving ESD Robustness of pMOS Device With Embedded SCR in 28-nm High-k/Metal Gate CMOS Process

Chun Yu Lin; Pin Hsin Chang; Rong Kun Chang

doi:10.1109/TED.2015.2396946

Improving ESD Robustness of pMOS Device With Embedded SCR in 28-nm High-k/Metal Gate CMOS Process

Chun Yu Lin, Pin Hsin Chang, Rong Kun Chang

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

13 Citations (Scopus)

Abstract

A pMOS device with an embedded silicon-controlled rectifier to improve its electrostatic discharge (ESD) robustness has been proposed and implemented in a 28-nm high-k/metal gate CMOS process. An additional p-type ESD implantation layer was added into the pMOS to realize the proposed device. The experimental results show that the proposed device has the advantages of high ESD robustness, low holding voltage, low parasitic capacitance, and good latchup immunity. With better performances, the proposed device was more suitable for ESD protection in a sub-50-nm CMOS process.

Original language	English
Article number	7038138
Pages (from-to)	1349-1352
Number of pages	4
Journal	IEEE Transactions on Electron Devices
Volume	62
Issue number	4
DOIs	https://doi.org/10.1109/TED.2015.2396946
Publication status	Published - 2015 Apr 1

Keywords

Electrostatic discharge (ESD)
pMOS
silicon-controlled rectifier (SCR)

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2015.2396946

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title = "Improving ESD Robustness of pMOS Device With Embedded SCR in 28-nm High-k/Metal Gate CMOS Process",

abstract = "A pMOS device with an embedded silicon-controlled rectifier to improve its electrostatic discharge (ESD) robustness has been proposed and implemented in a 28-nm high-k/metal gate CMOS process. An additional p-type ESD implantation layer was added into the pMOS to realize the proposed device. The experimental results show that the proposed device has the advantages of high ESD robustness, low holding voltage, low parasitic capacitance, and good latchup immunity. With better performances, the proposed device was more suitable for ESD protection in a sub-50-nm CMOS process.",

keywords = "Electrostatic discharge (ESD), pMOS, silicon-controlled rectifier (SCR)",

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AU - Lin, Chun Yu

AU - Chang, Pin Hsin

AU - Chang, Rong Kun

PY - 2015/4/1

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N2 - A pMOS device with an embedded silicon-controlled rectifier to improve its electrostatic discharge (ESD) robustness has been proposed and implemented in a 28-nm high-k/metal gate CMOS process. An additional p-type ESD implantation layer was added into the pMOS to realize the proposed device. The experimental results show that the proposed device has the advantages of high ESD robustness, low holding voltage, low parasitic capacitance, and good latchup immunity. With better performances, the proposed device was more suitable for ESD protection in a sub-50-nm CMOS process.

AB - A pMOS device with an embedded silicon-controlled rectifier to improve its electrostatic discharge (ESD) robustness has been proposed and implemented in a 28-nm high-k/metal gate CMOS process. An additional p-type ESD implantation layer was added into the pMOS to realize the proposed device. The experimental results show that the proposed device has the advantages of high ESD robustness, low holding voltage, low parasitic capacitance, and good latchup immunity. With better performances, the proposed device was more suitable for ESD protection in a sub-50-nm CMOS process.

KW - Electrostatic discharge (ESD)

KW - pMOS

KW - silicon-controlled rectifier (SCR)

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Improving ESD Robustness of pMOS Device With Embedded SCR in 28-nm High-k/Metal Gate CMOS Process

Abstract

Keywords

ASJC Scopus subject areas

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