Improved stacked-diode ESD protection in nanoscale CMOS technology

Chun Yu Lin, Meng Ting Lin

Research output: Contribution to journalLetter

2 Citations (Scopus)

Abstract

An improved electrostatic discharge (ESD) protection design, using stacked diodes with silicon-controlled rectifier (SCR), is presented to protect the radio-frequency (RF) integrated circuits in nanoscale CMOS process. Using the stacked diodes and SCR together to form diode-triggered-SCR-like paths, the critical ESD current paths are enhanced. The test circuits of the proposed ESD protection and conventional designs are compared in silicon chip. As verified in a 0.18 µm CMOS process, the proposed design exhibits a lower clamping voltage and higher current handling ability during ESD stress conditions, and sufficiently low parasitic capacitance and leakage current during normal circuit operating conditions. Therefore, the proposed design is suitable for ESD protection of RF circuits in low-voltage CMOS process.

Original languageEnglish
JournalIEICE Electronics Express
Volume14
Issue number13
DOIs
Publication statusPublished - 2017 Jan 1

Fingerprint

Electrostatic discharge
CMOS
Diodes
silicon controlled rectifiers
diodes
electrostatics
Thyristors
Networks (circuits)
radio frequencies
Electric potential
Silicon
Leakage currents
low voltage
integrated circuits
Integrated circuits
high current
leakage
Capacitance
capacitance
chips

Keywords

  • Electrostatic discharge (ESD)
  • Radio-frequency (RF)
  • Silicon-controlled rectifier (SCR)
  • Stacked diodes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

Improved stacked-diode ESD protection in nanoscale CMOS technology. / Lin, Chun Yu; Lin, Meng Ting.

In: IEICE Electronics Express, Vol. 14, No. 13, 01.01.2017.

Research output: Contribution to journalLetter

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N2 - An improved electrostatic discharge (ESD) protection design, using stacked diodes with silicon-controlled rectifier (SCR), is presented to protect the radio-frequency (RF) integrated circuits in nanoscale CMOS process. Using the stacked diodes and SCR together to form diode-triggered-SCR-like paths, the critical ESD current paths are enhanced. The test circuits of the proposed ESD protection and conventional designs are compared in silicon chip. As verified in a 0.18 µm CMOS process, the proposed design exhibits a lower clamping voltage and higher current handling ability during ESD stress conditions, and sufficiently low parasitic capacitance and leakage current during normal circuit operating conditions. Therefore, the proposed design is suitable for ESD protection of RF circuits in low-voltage CMOS process.

AB - An improved electrostatic discharge (ESD) protection design, using stacked diodes with silicon-controlled rectifier (SCR), is presented to protect the radio-frequency (RF) integrated circuits in nanoscale CMOS process. Using the stacked diodes and SCR together to form diode-triggered-SCR-like paths, the critical ESD current paths are enhanced. The test circuits of the proposed ESD protection and conventional designs are compared in silicon chip. As verified in a 0.18 µm CMOS process, the proposed design exhibits a lower clamping voltage and higher current handling ability during ESD stress conditions, and sufficiently low parasitic capacitance and leakage current during normal circuit operating conditions. Therefore, the proposed design is suitable for ESD protection of RF circuits in low-voltage CMOS process.

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