Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect

Ming Huei Lin; Yi Jia Shih; Chien Liu; Yu Chien Chiu; Chia Chi Fan; Guan Lin Liou; Chun Hu Cheng; Chun Yen Chang

doi:10.23919/SNW.2017.8242290

Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect

Ming Huei Lin, Yi Jia Shih, Chien Liu, Yu Chien Chiu, Chia Chi Fan, Guan Lin Liou, Chun Hu Cheng^*, Chun Yen Chang

^*Corresponding author for this work

Department of Mechatronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >10⁷. Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.

Original language	English
Title of host publication	2017 Silicon Nanoelectronics Workshop, SNW 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	47-48
Number of pages	2
ISBN (Electronic)	9784863486478
DOIs	https://doi.org/10.23919/SNW.2017.8242290
Publication status	Published - 2017 Dec 29
Event	22nd Silicon Nanoelectronics Workshop, SNW 2017 - Kyoto, Japan Duration: 2017 Jun 4 → 2017 Jun 5

Publication series

Name	2017 Silicon Nanoelectronics Workshop, SNW 2017
Volume	2017-January

Other

Other	22nd Silicon Nanoelectronics Workshop, SNW 2017
Country/Territory	Japan
City	Kyoto
Period	2017/06/04 → 2017/06/05

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.23919/SNW.2017.8242290

Cite this

Lin, M. H., Shih, Y. J., Liu, C., Chiu, Y. C., Fan, C. C., Liou, G. L., Cheng, C. H., & Chang, C. Y. (2017). Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect. In 2017 Silicon Nanoelectronics Workshop, SNW 2017 (pp. 47-48). Article 8242290 (2017 Silicon Nanoelectronics Workshop, SNW 2017; Vol. 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/SNW.2017.8242290

Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect. / Lin, Ming Huei; Shih, Yi Jia; Liu, Chien et al.
2017 Silicon Nanoelectronics Workshop, SNW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 47-48 8242290 (2017 Silicon Nanoelectronics Workshop, SNW 2017; Vol. 2017-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lin, MH, Shih, YJ, Liu, C, Chiu, YC, Fan, CC, Liou, GL, Cheng, CH & Chang, CY 2017, Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect. in 2017 Silicon Nanoelectronics Workshop, SNW 2017., 8242290, 2017 Silicon Nanoelectronics Workshop, SNW 2017, vol. 2017-January, Institute of Electrical and Electronics Engineers Inc., pp. 47-48, 22nd Silicon Nanoelectronics Workshop, SNW 2017, Kyoto, Japan, 2017/06/04. https://doi.org/10.23919/SNW.2017.8242290

Lin MH, Shih YJ, Liu C, Chiu YC, Fan CC, Liou GL et al. Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect. In 2017 Silicon Nanoelectronics Workshop, SNW 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 47-48. 8242290. (2017 Silicon Nanoelectronics Workshop, SNW 2017). doi: 10.23919/SNW.2017.8242290

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title = "Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect",

abstract = "This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >107. Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.",

author = "Lin, {Ming Huei} and Shih, {Yi Jia} and Chien Liu and Chiu, {Yu Chien} and Fan, {Chia Chi} and Liou, {Guan Lin} and Cheng, {Chun Hu} and Chang, {Chun Yen}",

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doi = "10.23919/SNW.2017.8242290",

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AU - Lin, Ming Huei

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AU - Chiu, Yu Chien

AU - Fan, Chia Chi

AU - Liou, Guan Lin

AU - Cheng, Chun Hu

AU - Chang, Chun Yen

PY - 2017/12/29

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N2 - This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >107. Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.

AB - This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >107. Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.

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Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect

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