Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect

Ming Huei Lin, Yi Jia Shih, Chien Liu, Yu Chien Chiu, Chia Chi Fan, Guan Lin Liou, Chun-Hu Cheng, Chun Yen Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >107. Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.

Original languageEnglish
Title of host publication2017 Silicon Nanoelectronics Workshop, SNW 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages47-48
Number of pages2
ISBN (Electronic)9784863486478
DOIs
Publication statusPublished - 2017 Dec 29
Event22nd Silicon Nanoelectronics Workshop, SNW 2017 - Kyoto, Japan
Duration: 2017 Jun 42017 Jun 5

Publication series

Name2017 Silicon Nanoelectronics Workshop, SNW 2017
Volume2017-January

Other

Other22nd Silicon Nanoelectronics Workshop, SNW 2017
CountryJapan
CityKyoto
Period17/6/417/6/5

Fingerprint

Stress measurement
Voltage measurement
Field effect transistors
Nanowires
Transistors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Lin, M. H., Shih, Y. J., Liu, C., Chiu, Y. C., Fan, C. C., Liou, G. L., ... Chang, C. Y. (2017). Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect. In 2017 Silicon Nanoelectronics Workshop, SNW 2017 (pp. 47-48). [8242290] (2017 Silicon Nanoelectronics Workshop, SNW 2017; Vol. 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/SNW.2017.8242290

Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect. / Lin, Ming Huei; Shih, Yi Jia; Liu, Chien; Chiu, Yu Chien; Fan, Chia Chi; Liou, Guan Lin; Cheng, Chun-Hu; Chang, Chun Yen.

2017 Silicon Nanoelectronics Workshop, SNW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 47-48 8242290 (2017 Silicon Nanoelectronics Workshop, SNW 2017; Vol. 2017-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lin, MH, Shih, YJ, Liu, C, Chiu, YC, Fan, CC, Liou, GL, Cheng, C-H & Chang, CY 2017, Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect. in 2017 Silicon Nanoelectronics Workshop, SNW 2017., 8242290, 2017 Silicon Nanoelectronics Workshop, SNW 2017, vol. 2017-January, Institute of Electrical and Electronics Engineers Inc., pp. 47-48, 22nd Silicon Nanoelectronics Workshop, SNW 2017, Kyoto, Japan, 17/6/4. https://doi.org/10.23919/SNW.2017.8242290
Lin MH, Shih YJ, Liu C, Chiu YC, Fan CC, Liou GL et al. Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect. In 2017 Silicon Nanoelectronics Workshop, SNW 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 47-48. 8242290. (2017 Silicon Nanoelectronics Workshop, SNW 2017). https://doi.org/10.23919/SNW.2017.8242290
Lin, Ming Huei ; Shih, Yi Jia ; Liu, Chien ; Chiu, Yu Chien ; Fan, Chia Chi ; Liou, Guan Lin ; Cheng, Chun-Hu ; Chang, Chun Yen. / Improved electrical characteristics and reliability of multi-stacking PNPN junctionless transistors using channel depletion effect. 2017 Silicon Nanoelectronics Workshop, SNW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 47-48 (2017 Silicon Nanoelectronics Workshop, SNW 2017).
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abstract = "This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >107. Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.",
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AB - This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >107. Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.

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