Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

Ming Dou Ker; Chun-Yu Lin; Chang Tang-Long Chang

doi:10.1109/IRPS.2011.5784565

Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

Ming Dou Ker, Chun-Yu Lin, Chang Tang-Long Chang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.

Original language	English
Title of host publication	2011 International Reliability Physics Symposium, IRPS 2011
DOIs	https://doi.org/10.1109/IRPS.2011.5784565
Publication status	Published - 2011 Jun 23
Event	49th International Reliability Physics Symposium, IRPS 2011 - Monterey, CA, United States Duration: 2011 Apr 10 → 2011 Apr 14

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
ISSN (Print)	1541-7026

Other

Other	49th International Reliability Physics Symposium, IRPS 2011
Country	United States
City	Monterey, CA
Period	11/4/10 → 11/4/14

Keywords

Charged-device model (CDM)
ESD
shielding line

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/IRPS.2011.5784565

Fingerprint Dive into the research topics of 'Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process'. Together they form a unique fingerprint.

Cite this

Ker, M. D., Lin, C-Y., & Tang-Long Chang, C. (2011). Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process. In 2011 International Reliability Physics Symposium, IRPS 2011 [5784565] (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/IRPS.2011.5784565

Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process. / Ker, Ming Dou; Lin, Chun-Yu; Tang-Long Chang, Chang.

2011 International Reliability Physics Symposium, IRPS 2011. 2011. 5784565 (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ker, MD, Lin, C-Y & Tang-Long Chang, C 2011, Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process. in 2011 International Reliability Physics Symposium, IRPS 2011., 5784565, IEEE International Reliability Physics Symposium Proceedings, 49th International Reliability Physics Symposium, IRPS 2011, Monterey, CA, United States, 11/4/10. https://doi.org/10.1109/IRPS.2011.5784565

@inproceedings{2d131bdb6f3d47bd8841bb8df5e595c1,

title = "Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process",

abstract = "The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.",

keywords = "Charged-device model (CDM), ESD, shielding line",

author = "Ker, {Ming Dou} and Chun-Yu Lin and {Tang-Long Chang}, Chang",

year = "2011",

month = jun,

day = "23",

doi = "10.1109/IRPS.2011.5784565",

language = "English",

isbn = "9781424491117",

series = "IEEE International Reliability Physics Symposium Proceedings",

booktitle = "2011 International Reliability Physics Symposium, IRPS 2011",

note = "49th International Reliability Physics Symposium, IRPS 2011 ; Conference date: 10-04-2011 Through 14-04-2011",

}

TY - GEN

T1 - Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

AU - Ker, Ming Dou

AU - Lin, Chun-Yu

AU - Tang-Long Chang, Chang

PY - 2011/6/23

Y1 - 2011/6/23

N2 - The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.

AB - The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.

KW - Charged-device model (CDM)

KW - ESD

KW - shielding line

UR - http://www.scopus.com/inward/record.url?scp=79959296002&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79959296002&partnerID=8YFLogxK

U2 - 10.1109/IRPS.2011.5784565

DO - 10.1109/IRPS.2011.5784565

M3 - Conference contribution

AN - SCOPUS:79959296002

SN - 9781424491117

T3 - IEEE International Reliability Physics Symposium Proceedings

BT - 2011 International Reliability Physics Symposium, IRPS 2011

T2 - 49th International Reliability Physics Symposium, IRPS 2011

Y2 - 10 April 2011 through 14 April 2011

ER -