TY - GEN
T1 - Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process
AU - Ker, Ming Dou
AU - Lin, Chun-Yu
AU - Tang-Long Chang, Chang
PY - 2011/6/23
Y1 - 2011/6/23
N2 - The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.
AB - The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.
KW - Charged-device model (CDM)
KW - ESD
KW - shielding line
UR - http://www.scopus.com/inward/record.url?scp=79959296002&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79959296002&partnerID=8YFLogxK
U2 - 10.1109/IRPS.2011.5784565
DO - 10.1109/IRPS.2011.5784565
M3 - Conference contribution
AN - SCOPUS:79959296002
SN - 9781424491117
T3 - IEEE International Reliability Physics Symposium Proceedings
BT - 2011 International Reliability Physics Symposium, IRPS 2011
T2 - 49th International Reliability Physics Symposium, IRPS 2011
Y2 - 10 April 2011 through 14 April 2011
ER -