Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

Ming Dou Ker, Chun-Yu Lin, Chang Tang-Long Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.

Original languageEnglish
Title of host publication2011 International Reliability Physics Symposium, IRPS 2011
DOIs
Publication statusPublished - 2011 Jun 23
Event49th International Reliability Physics Symposium, IRPS 2011 - Monterey, CA, United States
Duration: 2011 Apr 102011 Apr 14

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Other

Other49th International Reliability Physics Symposium, IRPS 2011
CountryUnited States
CityMonterey, CA
Period11/4/1011/4/14

Keywords

  • Charged-device model (CDM)
  • ESD
  • shielding line

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Ker, M. D., Lin, C-Y., & Tang-Long Chang, C. (2011). Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process. In 2011 International Reliability Physics Symposium, IRPS 2011 [5784565] (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/IRPS.2011.5784565