Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

Ming Dou Ker; Chun-Yu Lin; Chang Tang-Long Chang

doi:10.1109/IRPS.2011.5784565

Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

Ming Dou Ker^*, Chun-Yu Lin, Chang Tang-Long Chang

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.

Original language	English
Title of host publication	2011 International Reliability Physics Symposium, IRPS 2011
DOIs	https://doi.org/10.1109/IRPS.2011.5784565
Publication status	Published - 2011 Jun 23
Event	49th International Reliability Physics Symposium, IRPS 2011 - Monterey, CA, United States Duration: 2011 Apr 10 → 2011 Apr 14

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
ISSN (Print)	1541-7026

Other

Other	49th International Reliability Physics Symposium, IRPS 2011
Country/Territory	United States
City	Monterey, CA
Period	2011/04/10 → 2011/04/14

Keywords

Charged-device model (CDM)
ESD
shielding line

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/IRPS.2011.5784565

Cite this

Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process. / Ker, Ming Dou; Lin, Chun-Yu; Tang-Long Chang, Chang.

2011 International Reliability Physics Symposium, IRPS 2011. 2011. 5784565 (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ker, MD, Lin, C-Y & Tang-Long Chang, C 2011, Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process. in 2011 International Reliability Physics Symposium, IRPS 2011., 5784565, IEEE International Reliability Physics Symposium Proceedings, 49th International Reliability Physics Symposium, IRPS 2011, Monterey, CA, United States, 2011/04/10. https://doi.org/10.1109/IRPS.2011.5784565

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abstract = "The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.",

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author = "Ker, {Ming Dou} and Chun-Yu Lin and {Tang-Long Chang}, Chang",

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AB - The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.

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Y2 - 10 April 2011 through 14 April 2011

ER -

Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

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Keywords

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