Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process

Ming Dou Ker; Yong Ru Wen; Wen Yi Chen; Chun Yu Lin

doi:10.1109/ISNE.2010.5669188

Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process

Ming Dou Ker^*, Yong Ru Wen, Wen Yi Chen, Chun Yu Lin

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Citations (Scopus)

Abstract

Electrostatic discharge (ESD) is an inevitable event in CMOS integrated circuits. Layout structure is one of the im portant factors that affect ESD robustness of MOS transistors. In this work, the impact of inserting additional layout pickups to ESD robustness of both multi-finger NMOS and PMOS transistors has been studied in a 90-nm CMOS process. Measurement results have shown that multi-finger MOS transistors without additional pickup inserted into their source regions can sustain a higher ESD protection level at the same effective device dimension.

Original language	English
Title of host publication	2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
Pages	100-103
Number of pages	4
DOIs	https://doi.org/10.1109/ISNE.2010.5669188
Publication status	Published - 2010
Externally published	Yes
Event	2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, Taiwan Duration: 2010 Nov 18 → 2010 Nov 19

Publication series

Name	2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Other

Other	2010 International Symposium on Next-Generation Electronics, ISNE 2010
Country/Territory	Taiwan
City	Kaohsiung
Period	2010/11/18 → 2010/11/19

Keywords

Electrostatic discharge (ESD)
Pickup

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISNE.2010.5669188

Cite this

Ker, M. D., Wen, Y. R., Chen, W. Y., & Lin, C. Y. (2010). Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process. In 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program (pp. 100-103). Article 5669188 (2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program). https://doi.org/10.1109/ISNE.2010.5669188

Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process. / Ker, Ming Dou; Wen, Yong Ru; Chen, Wen Yi et al.
2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program. 2010. p. 100-103 5669188 (2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ker, MD, Wen, YR, Chen, WY & Lin, CY 2010, Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process. in 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program., 5669188, 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program, pp. 100-103, 2010 International Symposium on Next-Generation Electronics, ISNE 2010, Kaohsiung, Taiwan, 2010/11/18. https://doi.org/10.1109/ISNE.2010.5669188

Ker MD, Wen YR, Chen WY, Lin CY. Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process. In 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program. 2010. p. 100-103. 5669188. (2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program). doi: 10.1109/ISNE.2010.5669188

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abstract = "Electrostatic discharge (ESD) is an inevitable event in CMOS integrated circuits. Layout structure is one of the im portant factors that affect ESD robustness of MOS transistors. In this work, the impact of inserting additional layout pickups to ESD robustness of both multi-finger NMOS and PMOS transistors has been studied in a 90-nm CMOS process. Measurement results have shown that multi-finger MOS transistors without additional pickup inserted into their source regions can sustain a higher ESD protection level at the same effective device dimension.",

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AB - Electrostatic discharge (ESD) is an inevitable event in CMOS integrated circuits. Layout structure is one of the im portant factors that affect ESD robustness of MOS transistors. In this work, the impact of inserting additional layout pickups to ESD robustness of both multi-finger NMOS and PMOS transistors has been studied in a 90-nm CMOS process. Measurement results have shown that multi-finger MOS transistors without additional pickup inserted into their source regions can sustain a higher ESD protection level at the same effective device dimension.

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Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process

Abstract

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Keywords

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