Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices

J. Y. Wei, S. Maikap, M. H. Lee, C. C. Lee, C. W. Liu*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

14 Citations (Scopus)


Due to the Fermi level pinning effect on the hole confinement at the valence band offset, the capacitance-voltage (C-V) characteristics of NMOS capacitor exhibit more obvious plateau than that of PMOS capacitor, demonstrated by both experimental and simulated results. Using device simulation, the ratio of hole density at the oxide/strained-Si interface to that at the strained-Si/relaxed SiGe interface for both N and PMOSFETs is investigated. The much higher hole density ratio in PMOSFETs than that in NMOSFETs also reveals the Fermi level pinning effect.

Original languageEnglish
Pages (from-to)109-113
Number of pages5
JournalSolid-State Electronics
Issue number2
Publication statusPublished - 2006 Feb
Externally publishedYes


  • Device simulation
  • Hole confinement
  • MOS C-V
  • Pinning effect
  • Strain

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


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