Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices

J. Y. Wei, S. Maikap, M. H. Lee, C. C. Lee, C. W. Liu

    Research output: Contribution to journalArticle

    14 Citations (Scopus)

    Abstract

    Due to the Fermi level pinning effect on the hole confinement at the valence band offset, the capacitance-voltage (C-V) characteristics of NMOS capacitor exhibit more obvious plateau than that of PMOS capacitor, demonstrated by both experimental and simulated results. Using device simulation, the ratio of hole density at the oxide/strained-Si interface to that at the strained-Si/relaxed SiGe interface for both N and PMOSFETs is investigated. The much higher hole density ratio in PMOSFETs than that in NMOSFETs also reveals the Fermi level pinning effect.

    Original languageEnglish
    Pages (from-to)109-113
    Number of pages5
    JournalSolid-State Electronics
    Volume50
    Issue number2
    DOIs
    Publication statusPublished - 2006 Feb 1

    Fingerprint

    Fermi level
    Heterojunctions
    heterojunctions
    Capacitors
    capacitors
    Valence bands
    Oxides
    Capacitance
    capacitance-voltage characteristics
    plateaus
    Electric potential
    valence
    oxides
    simulation

    Keywords

    • Device simulation
    • Hole confinement
    • MOS C-V
    • Pinning effect
    • Strain

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Condensed Matter Physics
    • Electrical and Electronic Engineering
    • Materials Chemistry

    Cite this

    Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices. / Wei, J. Y.; Maikap, S.; Lee, M. H.; Lee, C. C.; Liu, C. W.

    In: Solid-State Electronics, Vol. 50, No. 2, 01.02.2006, p. 109-113.

    Research output: Contribution to journalArticle

    Wei, J. Y. ; Maikap, S. ; Lee, M. H. ; Lee, C. C. ; Liu, C. W. / Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices. In: Solid-State Electronics. 2006 ; Vol. 50, No. 2. pp. 109-113.
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