High throughput and low area cost FPGA-based signature match circuit for network intrusion detection

Wen Jyi Hwang; Chien Min Ou; Ying Nan Shih; Chia Tien dan Lo

doi:10.1080/02533839.2009.9671520

High throughput and low area cost FPGA-based signature match circuit for network intrusion detection

Wen Jyi Hwang, Chien Min Ou^*, Ying Nan Shih, Chia Tien dan Lo

^*Corresponding author for this work

Department of Computer Science and Information Engineering

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

A novel FPGA-based signature match circuit serving as the core of a hardware-based network intrusion detection system (NIDS) is presented in this paper. The circuit is based on simple shift registers and signature decoders for efficient hardware signature matches. As compared with related work, experimental results show that the proposed work achieves high throughput and uses few hardware resources in the FPGA implementations of NIDS systems.

Original language	English
Pages (from-to)	397-405
Number of pages	9
Journal	Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an
Volume	32
Issue number	3
DOIs	https://doi.org/10.1080/02533839.2009.9671520
Publication status	Published - 2009

Keywords

FPGA implementation
Network intrusion detection system
Pattern matching

ASJC Scopus subject areas

General Engineering

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10.1080/02533839.2009.9671520

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High throughput and low area cost FPGA-based signature match circuit for network intrusion detection. / Hwang, Wen Jyi; Ou, Chien Min; Shih, Ying Nan et al.
In: Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an, Vol. 32, No. 3, 2009, p. 397-405.

Research output: Contribution to journal › Article › peer-review

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High throughput and low area cost FPGA-based signature match circuit for network intrusion detection

Abstract

Keywords

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