High throughput 32-bit AES implementation in FPGA

Chi Jeng Chang; Chi Wu Huang; Kuo Huang Chang; Yi G. Chen; Chung Cheng Hsieh

doi:10.1109/APCCAS.2008.4746393

High throughput 32-bit AES implementation in FPGA

Chi Jeng Chang^*, Chi Wu Huang, Kuo Huang Chang, Yi G. Chen, Chung Cheng Hsieh

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

20 Citations (Scopus)

Abstract

Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature[9].

Original language	English
Title of host publication	Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Pages	1806-1809
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2008.4746393
Publication status	Published - 2008
Externally published	Yes
Event	APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, China Duration: 2008 Nov 30 → 2008 Dec 3

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other	APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Country/Territory	China
City	Macao
Period	2008/11/30 → 2008/12/03

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APCCAS.2008.4746393

Cite this

Chang, C. J., Huang, C. W., Chang, K. H., Chen, Y. G., & Hsieh, C. C. (2008). High throughput 32-bit AES implementation in FPGA. In Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (pp. 1806-1809). Article 4746393 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2008.4746393

High throughput 32-bit AES implementation in FPGA. / Chang, Chi Jeng; Huang, Chi Wu; Chang, Kuo Huang et al.
Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. 2008. p. 1806-1809 4746393 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chang, CJ, Huang, CW, Chang, KH, Chen, YG & Hsieh, CC 2008, High throughput 32-bit AES implementation in FPGA. in Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems., 4746393, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 1806-1809, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, 2008/11/30. https://doi.org/10.1109/APCCAS.2008.4746393

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author = "Chang, {Chi Jeng} and Huang, {Chi Wu} and Chang, {Kuo Huang} and Chen, {Yi G.} and Hsieh, {Chung Cheng}",

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AB - Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature[9].

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High throughput 32-bit AES implementation in FPGA

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