High throughput 32-bit AES implementation in FPGA

Chi Jeng Chang, Chi Wu Huang, Kuo Huang Chang, Yi G. Chen, Chung Cheng Hsieh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature[9].

Original languageEnglish
Title of host publicationProceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Pages1806-1809
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 1
EventAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, China
Duration: 2008 Nov 302008 Dec 3

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

OtherAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
CountryChina
CityMacao
Period08/11/3008/12/3

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Chang, C. J., Huang, C. W., Chang, K. H., Chen, Y. G., & Hsieh, C. C. (2008). High throughput 32-bit AES implementation in FPGA. In Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (pp. 1806-1809). [4746393] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2008.4746393