High speed negative capacitance ferroelectric memory

Chun Yen Chang, Chia Chi Fan, Chien Liu, Yu Chien Chiu, Chun Hu Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This work experimentally demonstrated a one-transistor ferroelectric versatile memory with the multi-technique integration of negative-capacitance mechanism, ferroelectric polarization effect and metal-strained engineering. The negative-capacitance versatile memory featured a steep sub-60mV/dec subthreshold swing, fast 20-ns switching speed and long 1012 cycled endurance. We successfully demonstrated that the metal-gate-induced strain could help to improve ferroelectric phase transformation. The excellent endurance characteristics could be ascribed to efficient ferroelectric negative-capacitance switching under low program/erase voltages.

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
EditorsYajie Qin, Zhiliang Hong, Ting-Ao Tang
PublisherIEEE Computer Society
Number of pages5
ISBN (Electronic)9781509066247
Publication statusPublished - 2017 Jul 1
Event12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China
Duration: 2017 Oct 252017 Oct 28

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X


Conference12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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