@inproceedings{f6c814578b2349879ac474e301a4a535,
title = "High speed negative capacitance ferroelectric memory",
abstract = " This work experimentally demonstrated a one-transistor ferroelectric versatile memory with the multi-technique integration of negative-capacitance mechanism, ferroelectric polarization effect and metal-strained engineering. The negative-capacitance versatile memory featured a steep sub-60mV/dec subthreshold swing, fast 20-ns switching speed and long 10 12 cycled endurance. We successfully demonstrated that the metal-gate-induced strain could help to improve ferroelectric phase transformation. The excellent endurance characteristics could be ascribed to efficient ferroelectric negative-capacitance switching under low program/erase voltages. ",
author = "Chang, {Chun Yen} and Fan, {Chia Chi} and Chien Liu and Chiu, {Yu Chien} and Cheng, {Chun Hu}",
note = "Funding Information: We would like to thank instrument support from National Nano Device Laboratories (NDL) and Nano Facility Center (NFC), Taiwan, R.O.C. Publisher Copyright: {\textcopyright} 2017 IEEE.; 12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 ; Conference date: 25-10-2017 Through 28-10-2017",
year = "2018",
month = jan,
day = "8",
doi = "10.1109/ASICON.2017.8252397",
language = "English",
series = "Proceedings of International Conference on ASIC",
publisher = "IEEE Computer Society",
pages = "1--5",
editor = "Yajie Qin and Ting-Ao Tang and Zhiliang Hong",
booktitle = "Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017",
}