High speed c-means clustering in reconfigurable hardware

Wen Jyi Hwang*, Chih Chieh Hsu, Hui Ya Li, Sheng Kai Weng, Tsung Yi Yu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


A novel hardware architecture for c-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. A simple divider circuit based on lookup table, multiplication and shift operations is employed for reducing both the area cost and latency for centroid computation. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on an FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for c-means design.

Original languageEnglish
Pages (from-to)237-246
Number of pages10
JournalMicroprocessors and Microsystems
Issue number6
Publication statusPublished - 2010 Oct


  • C-Means
  • Data clustering
  • FPGA
  • System on programmable chip

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence


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