High speed c-means clustering in reconfigurable hardware

Wen Jyi Hwang, Chih Chieh Hsu, Hui Ya Li, Sheng Kai Weng, Tsung Yi Yu

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

A novel hardware architecture for c-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. A simple divider circuit based on lookup table, multiplication and shift operations is employed for reducing both the area cost and latency for centroid computation. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on an FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for c-means design.

Original languageEnglish
Pages (from-to)237-246
Number of pages10
JournalMicroprocessors and Microsystems
Volume34
Issue number6
DOIs
Publication statusPublished - 2010 Oct 1

Fingerprint

Reconfigurable hardware
Computer hardware
Table lookup
Particle accelerators
Program processors
Field programmable gate arrays (FPGA)
Costs
Networks (circuits)

Keywords

  • C-Means
  • Data clustering
  • FPGA
  • System on programmable chip

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence

Cite this

High speed c-means clustering in reconfigurable hardware. / Hwang, Wen Jyi; Hsu, Chih Chieh; Li, Hui Ya; Weng, Sheng Kai; Yu, Tsung Yi.

In: Microprocessors and Microsystems, Vol. 34, No. 6, 01.10.2010, p. 237-246.

Research output: Contribution to journalArticle

Hwang, Wen Jyi ; Hsu, Chih Chieh ; Li, Hui Ya ; Weng, Sheng Kai ; Yu, Tsung Yi. / High speed c-means clustering in reconfigurable hardware. In: Microprocessors and Microsystems. 2010 ; Vol. 34, No. 6. pp. 237-246.
@article{52c6ff5e8be246a2ae89f7506b998480,
title = "High speed c-means clustering in reconfigurable hardware",
abstract = "A novel hardware architecture for c-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. A simple divider circuit based on lookup table, multiplication and shift operations is employed for reducing both the area cost and latency for centroid computation. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on an FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for c-means design.",
keywords = "C-Means, Data clustering, FPGA, System on programmable chip",
author = "Hwang, {Wen Jyi} and Hsu, {Chih Chieh} and Li, {Hui Ya} and Weng, {Sheng Kai} and Yu, {Tsung Yi}",
year = "2010",
month = "10",
day = "1",
doi = "10.1016/j.micpro.2010.05.001",
language = "English",
volume = "34",
pages = "237--246",
journal = "Microprocessors and Microsystems",
issn = "0141-9331",
publisher = "Elsevier",
number = "6",

}

TY - JOUR

T1 - High speed c-means clustering in reconfigurable hardware

AU - Hwang, Wen Jyi

AU - Hsu, Chih Chieh

AU - Li, Hui Ya

AU - Weng, Sheng Kai

AU - Yu, Tsung Yi

PY - 2010/10/1

Y1 - 2010/10/1

N2 - A novel hardware architecture for c-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. A simple divider circuit based on lookup table, multiplication and shift operations is employed for reducing both the area cost and latency for centroid computation. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on an FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for c-means design.

AB - A novel hardware architecture for c-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. A simple divider circuit based on lookup table, multiplication and shift operations is employed for reducing both the area cost and latency for centroid computation. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on an FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for c-means design.

KW - C-Means

KW - Data clustering

KW - FPGA

KW - System on programmable chip

UR - http://www.scopus.com/inward/record.url?scp=77954212292&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77954212292&partnerID=8YFLogxK

U2 - 10.1016/j.micpro.2010.05.001

DO - 10.1016/j.micpro.2010.05.001

M3 - Article

AN - SCOPUS:77954212292

VL - 34

SP - 237

EP - 246

JO - Microprocessors and Microsystems

JF - Microprocessors and Microsystems

SN - 0141-9331

IS - 6

ER -