High performance 50 nm CMOS devices for microprocessor and embedded processor core applications

Shih Fen Huang; Chih Yung Lin; Yu Shyang Huang; Thomas Schafbauer; Manfred Eller; Yao Ching Cheng; Shui Ming Cheng; Sandrine Sportouch; Wei Jin; Nivo Rovedo; Andreas Grassmann; Yimin Huang; James Brighten; Chuan H. Liu; Birgit Von Ehrenwall; Norman Chen; Jia Chen; O. Seo Park; Martin Commons; Alan Thomas; Ming Tsan Lee; Steward Rauch; Larry Clevenger; Erdem Kaltalioglu; Pak Leung; Jenkon Chen; Thomas Schiml; Clement Wann

doi:10.1109/IEDM.2001.979474

High performance 50 nm CMOS devices for microprocessor and embedded processor core applications

Shih Fen Huang
, Chih Yung Lin
, Yu Shyang Huang
, Thomas Schafbauer
, Manfred Eller
, Yao Ching Cheng
, Shui Ming Cheng
, Sandrine Sportouch
, Wei Jin
, Nivo Rovedo
, Andreas Grassmann
, Yimin Huang
, James Brighten
, Chuan H. Liu
, Birgit Von Ehrenwall
, Norman Chen
, Jia Chen
, O. Seo Park
, Martin Commons
, Alan Thomas

Ming Tsan Lee, Steward Rauch, Larry Clevenger, Erdem Kaltalioglu, Pak Leung, Jenkon Chen, Thomas Schiml, Clement Wann

Research output: Contribution to journal › Article › peer-review

44 Citations (Scopus)

Abstract

50 nm CMOS transistors for high performance and low active power applications are presented. Good short-channel effect control is achieved down to 35 nm gate length. These transistors will be incorporated in a leading edge 100 nm technology, with optimized triple well, nitrided oxide gate dielectrics, 193-nm lithography, 9-level hierarchical Cu interconnects, and low-k dielectrics. These high performance transistors have the best current drive at a given leakage current reported in the literature.

Original language	English
Pages (from-to)	237-240
Number of pages	4
Journal	Technical Digest-International Electron Devices Meeting
DOIs	https://doi.org/10.1109/IEDM.2001.979474
Publication status	Published - 2001
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Materials Chemistry
Electrical and Electronic Engineering

Access to Document

10.1109/IEDM.2001.979474

Cite this

Huang, S. F., Lin, C. Y., Huang, Y. S., Schafbauer, T., Eller, M., Cheng, Y. C., Cheng, S. M., Sportouch, S., Jin, W., Rovedo, N., Grassmann, A., Huang, Y., Brighten, J., Liu, C. H., Von Ehrenwall, B., Chen, N., Chen, J., Park, O. S., Commons, M., ... Wann, C. (2001). High performance 50 nm CMOS devices for microprocessor and embedded processor core applications. Technical Digest-International Electron Devices Meeting, 237-240. https://doi.org/10.1109/IEDM.2001.979474

Huang, SF, Lin, CY, Huang, YS, Schafbauer, T, Eller, M, Cheng, YC, Cheng, SM, Sportouch, S, Jin, W, Rovedo, N, Grassmann, A, Huang, Y, Brighten, J, Liu, CH, Von Ehrenwall, B, Chen, N, Chen, J, Park, OS, Commons, M, Thomas, A, Lee, MT, Rauch, S, Clevenger, L, Kaltalioglu, E, Leung, P, Chen, J, Schiml, T & Wann, C 2001, 'High performance 50 nm CMOS devices for microprocessor and embedded processor core applications', Technical Digest-International Electron Devices Meeting, pp. 237-240. https://doi.org/10.1109/IEDM.2001.979474

@article{a6eaa9e479e24aeabb64b43c650a0aca,

title = "High performance 50 nm CMOS devices for microprocessor and embedded processor core applications",

abstract = "50 nm CMOS transistors for high performance and low active power applications are presented. Good short-channel effect control is achieved down to 35 nm gate length. These transistors will be incorporated in a leading edge 100 nm technology, with optimized triple well, nitrided oxide gate dielectrics, 193-nm lithography, 9-level hierarchical Cu interconnects, and low-k dielectrics. These high performance transistors have the best current drive at a given leakage current reported in the literature.",

author = "Huang, \{Shih Fen\} and Lin, \{Chih Yung\} and Huang, \{Yu Shyang\} and Thomas Schafbauer and Manfred Eller and Cheng, \{Yao Ching\} and Cheng, \{Shui Ming\} and Sandrine Sportouch and Wei Jin and Nivo Rovedo and Andreas Grassmann and Yimin Huang and James Brighten and Liu, \{Chuan H.\} and \{Von Ehrenwall\}, Birgit and Norman Chen and Jia Chen and Park, \{O. Seo\} and Martin Commons and Alan Thomas and Lee, \{Ming Tsan\} and Steward Rauch and Larry Clevenger and Erdem Kaltalioglu and Pak Leung and Jenkon Chen and Thomas Schiml and Clement Wann",

year = "2001",

doi = "10.1109/IEDM.2001.979474",

language = "English",

pages = "237--240",

journal = "Technical Digest-International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - High performance 50 nm CMOS devices for microprocessor and embedded processor core applications

AU - Huang, Shih Fen

AU - Lin, Chih Yung

AU - Huang, Yu Shyang

AU - Schafbauer, Thomas

AU - Eller, Manfred

AU - Cheng, Yao Ching

AU - Cheng, Shui Ming

AU - Sportouch, Sandrine

AU - Jin, Wei

AU - Rovedo, Nivo

AU - Grassmann, Andreas

AU - Huang, Yimin

AU - Brighten, James

AU - Liu, Chuan H.

AU - Von Ehrenwall, Birgit

AU - Chen, Norman

AU - Chen, Jia

AU - Park, O. Seo

AU - Commons, Martin

AU - Thomas, Alan

AU - Lee, Ming Tsan

AU - Rauch, Steward

AU - Clevenger, Larry

AU - Kaltalioglu, Erdem

AU - Leung, Pak

AU - Chen, Jenkon

AU - Schiml, Thomas

AU - Wann, Clement

PY - 2001

Y1 - 2001

N2 - 50 nm CMOS transistors for high performance and low active power applications are presented. Good short-channel effect control is achieved down to 35 nm gate length. These transistors will be incorporated in a leading edge 100 nm technology, with optimized triple well, nitrided oxide gate dielectrics, 193-nm lithography, 9-level hierarchical Cu interconnects, and low-k dielectrics. These high performance transistors have the best current drive at a given leakage current reported in the literature.

AB - 50 nm CMOS transistors for high performance and low active power applications are presented. Good short-channel effect control is achieved down to 35 nm gate length. These transistors will be incorporated in a leading edge 100 nm technology, with optimized triple well, nitrided oxide gate dielectrics, 193-nm lithography, 9-level hierarchical Cu interconnects, and low-k dielectrics. These high performance transistors have the best current drive at a given leakage current reported in the literature.

UR - https://www.scopus.com/pages/publications/17544404834

UR - https://www.scopus.com/pages/publications/17544404834#tab=citedBy

U2 - 10.1109/IEDM.2001.979474

DO - 10.1109/IEDM.2001.979474

M3 - Article

AN - SCOPUS:17544404834

SN - 0163-1918

SP - 237

EP - 240

JO - Technical Digest-International Electron Devices Meeting

JF - Technical Digest-International Electron Devices Meeting

ER -

High performance 50 nm CMOS devices for microprocessor and embedded processor core applications

Abstract

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this