High performance 50 nm CMOS devices for microprocessor and embedded processor core applications

Shih Fen Huang, Chih Yung Lin, Yu Shyang Huang, Thomas Schafbauer, Manfred Eller, Yao Ching Cheng, Shui Ming Cheng, Sandrine Sportouch, Wei Jin, Nivo Rovedo, Andreas Grassmann, Yimin Huang, James Brighten, Chuan H. Liu, Birgit Von Ehrenwall, Norman Chen, Jia Chen, O. Seo Park, Martin Commons, Alan ThomasMing Tsan Lee, Steward Rauch, Larry Clevenger, Erdem Kaltalioglu, Pak Leung, Jenkon Chen, Thomas Schiml, Clement Wann

Research output: Contribution to journalArticle

39 Citations (Scopus)

Abstract

50 nm CMOS transistors for high performance and low active power applications are presented. Good short-channel effect control is achieved down to 35 nm gate length. These transistors will be incorporated in a leading edge 100 nm technology, with optimized triple well, nitrided oxide gate dielectrics, 193-nm lithography, 9-level hierarchical Cu interconnects, and low-k dielectrics. These high performance transistors have the best current drive at a given leakage current reported in the literature.

Original languageEnglish
Pages (from-to)237-240
Number of pages4
JournalTechnical Digest-International Electron Devices Meeting
DOIs
Publication statusPublished - 2001 Jan 1

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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  • Cite this

    Huang, S. F., Lin, C. Y., Huang, Y. S., Schafbauer, T., Eller, M., Cheng, Y. C., Cheng, S. M., Sportouch, S., Jin, W., Rovedo, N., Grassmann, A., Huang, Y., Brighten, J., Liu, C. H., Von Ehrenwall, B., Chen, N., Chen, J., Park, O. S., Commons, M., ... Wann, C. (2001). High performance 50 nm CMOS devices for microprocessor and embedded processor core applications. Technical Digest-International Electron Devices Meeting, 237-240. https://doi.org/10.1109/IEDM.2001.979474