Hardware/software co-design for particle swarm optimization algorithm

Shih An Li, Chen Chien Hsu*, Ching Chang Wong, Chia Jun Yu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

34 Citations (Scopus)


This paper presents a hardware/software (HW/SW) co-design approach using SOPC technique and pipeline design method to improve design flexibility and execution performance of particle swarm optimization (PSO) for embedded applications. Based on modular design architecture, a Particle Updating Accelerator module via hardware implementation for updating velocity and position of particles and a Fitness Evaluation module implemented either on a soft-cored processor or Field Programmable Gate Array (FPGA) for evaluating the objective functions are respectively designed to work closely together to carry out the evolution process at different design stages. Thanks to the design flexibility, the proposed approach can tackle various optimization problems of embedded applications without the need for hardware redesign. To further improve the execution performance of the PSO, a hardware random number generator (RNG) is also designed in this paper in addition to a particle re-initialization scheme to promote exploration search during the optimization process. Experimental results have demonstrated that the proposed HW/SW co-design approach for PSO algorithms has good efficiency for obtaining high-quality solutions for embedded applications.

Original languageEnglish
Pages (from-to)4582-4596
Number of pages15
JournalInformation Sciences
Issue number20
Publication statusPublished - 2011 Oct 15


  • Field Programmable Gate Array (FPGA)
  • HW/SW co-design
  • Particle swarm optimization (PSO)
  • System on a programmable chip (SOPC)

ASJC Scopus subject areas

  • Software
  • Control and Systems Engineering
  • Theoretical Computer Science
  • Computer Science Applications
  • Information Systems and Management
  • Artificial Intelligence


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