Hardware implementation of κ-winner-take-all neural network with on-chip learning

Hui Ya Li; Chien Min Ou; Yi Tsan Hung; Wen Jyi Hwang; Chia Lung Hung

doi:10.1109/CSE.2010.51

Hardware implementation of κ-winner-take-all neural network with on-chip learning

Hui Ya Li^*, Chien Min Ou, Yi Tsan Hung, Wen Jyi Hwang, Chia Lung Hung

^*Corresponding author for this work

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

This paper presents a novel pipelined architecture of the competitive learning (CL) algorithm with κ-winners-take-all activation. The architecture employs a codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. An efficient pipeline architecture is then designed based on the codeword swapping scheme for enhancing the throughput. The CPU time of the NIOS processor executing the CL training with the proposed architecture as an accelerator is measured. Experiment results show that the CPU time is lower than that of other hardware or software implementations running the CL training program with or without the support of custom hardware.

Original language	English
Title of host publication	Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010
Pages	340-345
Number of pages	6
DOIs	https://doi.org/10.1109/CSE.2010.51
Publication status	Published - 2010
Event	2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010 - Hong Kong, China Duration: 2010 Dec 11 → 2010 Dec 13

Publication series

Name	Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010

Other

Other	2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010
Country/Territory	China
City	Hong Kong
Period	2010/12/11 → 2010/12/13

Keywords

Competitive learning
FPGA
On-chip learning
Reconfigurable computing
κ-winners-take-all

ASJC Scopus subject areas

Computer Science (miscellaneous)

Access to Document

10.1109/CSE.2010.51

Cite this

Li, H. Y., Ou, C. M., Hung, Y. T., Hwang, W. J., & Hung, C. L. (2010). Hardware implementation of κ-winner-take-all neural network with on-chip learning. In Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010 (pp. 340-345). Article 5692497 (Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010). https://doi.org/10.1109/CSE.2010.51

Hardware implementation of κ-winner-take-all neural network with on-chip learning. / Li, Hui Ya; Ou, Chien Min; Hung, Yi Tsan et al.
Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010. 2010. p. 340-345 5692497 (Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, HY, Ou, CM, Hung, YT, Hwang, WJ & Hung, CL 2010, Hardware implementation of κ-winner-take-all neural network with on-chip learning. in Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010., 5692497, Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010, pp. 340-345, 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010, Hong Kong, China, 2010/12/11. https://doi.org/10.1109/CSE.2010.51

Li HY, Ou CM, Hung YT, Hwang WJ, Hung CL. Hardware implementation of κ-winner-take-all neural network with on-chip learning. In Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010. 2010. p. 340-345. 5692497. (Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010). doi: 10.1109/CSE.2010.51

@inproceedings{04f032b45dfd45da926d2d08d728621e,

title = "Hardware implementation of κ-winner-take-all neural network with on-chip learning",

abstract = "This paper presents a novel pipelined architecture of the competitive learning (CL) algorithm with κ-winners-take-all activation. The architecture employs a codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. An efficient pipeline architecture is then designed based on the codeword swapping scheme for enhancing the throughput. The CPU time of the NIOS processor executing the CL training with the proposed architecture as an accelerator is measured. Experiment results show that the CPU time is lower than that of other hardware or software implementations running the CL training program with or without the support of custom hardware.",

keywords = "Competitive learning, FPGA, On-chip learning, Reconfigurable computing, κ-winners-take-all",

author = "Li, {Hui Ya} and Ou, {Chien Min} and Hung, {Yi Tsan} and Hwang, {Wen Jyi} and Hung, {Chia Lung}",

year = "2010",

doi = "10.1109/CSE.2010.51",

language = "English",

isbn = "9780769543239",

series = "Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010",

pages = "340--345",

booktitle = "Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010",

note = "2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010 ; Conference date: 11-12-2010 Through 13-12-2010",

}

TY - GEN

T1 - Hardware implementation of κ-winner-take-all neural network with on-chip learning

AU - Li, Hui Ya

AU - Ou, Chien Min

AU - Hung, Yi Tsan

AU - Hwang, Wen Jyi

AU - Hung, Chia Lung

PY - 2010

Y1 - 2010

N2 - This paper presents a novel pipelined architecture of the competitive learning (CL) algorithm with κ-winners-take-all activation. The architecture employs a codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. An efficient pipeline architecture is then designed based on the codeword swapping scheme for enhancing the throughput. The CPU time of the NIOS processor executing the CL training with the proposed architecture as an accelerator is measured. Experiment results show that the CPU time is lower than that of other hardware or software implementations running the CL training program with or without the support of custom hardware.

AB - This paper presents a novel pipelined architecture of the competitive learning (CL) algorithm with κ-winners-take-all activation. The architecture employs a codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. An efficient pipeline architecture is then designed based on the codeword swapping scheme for enhancing the throughput. The CPU time of the NIOS processor executing the CL training with the proposed architecture as an accelerator is measured. Experiment results show that the CPU time is lower than that of other hardware or software implementations running the CL training program with or without the support of custom hardware.

KW - Competitive learning

KW - FPGA

KW - On-chip learning

KW - Reconfigurable computing

KW - κ-winners-take-all

UR - http://www.scopus.com/inward/record.url?scp=79951595575&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79951595575&partnerID=8YFLogxK

U2 - 10.1109/CSE.2010.51

DO - 10.1109/CSE.2010.51

M3 - Conference contribution

AN - SCOPUS:79951595575

SN - 9780769543239

T3 - Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010

SP - 340

EP - 345

BT - Proceedings - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010

T2 - 2010 13th IEEE International Conference on Computational Science and Engineering, CSE 2010

Y2 - 11 December 2010 through 13 December 2010

ER -

Hardware implementation of κ-winner-take-all neural network with on-chip learning

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this