Hardware Architecture of Parallel Video Halftoning for Electronic Papers

Wen Chung Kao*, Tsai Ting Yen, Ji Lun Ho

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A modified direct binary search (DBS) algorithm which minimizes the flickers on the stationary regions has been proposed for electronic paper (ePaper) in our previous work. Acceptable video quality can be achieved in one iteration, but the high time complexity of DBS algorithm still leads to the difficulty of implementing it on an ePaper system. In general, the ePaper is equipped with a low-power microcontroller. It is infeasible to perform real-time video halftoning on such a hardware platform. This paper presents a novel hardware architecture based on a parallel video halftoning algorithm, for electronic papers. This halftoning engine performs DBS for four pixels in a macro block or in different macro blocks parallelly.

Original languageEnglish
Title of host publication2023 International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2023 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages699-700
Number of pages2
ISBN (Electronic)9798350324174
DOIs
Publication statusPublished - 2023
Event2023 International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2023 - Pingtung, Taiwan
Duration: 2023 Jul 172023 Jul 19

Publication series

Name2023 International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2023 - Proceedings

Conference

Conference2023 International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2023
Country/TerritoryTaiwan
CityPingtung
Period2023/07/172023/07/19

ASJC Scopus subject areas

  • Artificial Intelligence
  • Human-Computer Interaction
  • Information Systems
  • Information Systems and Management
  • Electrical and Electronic Engineering
  • Media Technology
  • Instrumentation

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