A general interconnection network is proposed, taking into account locality of traffic. The network has log2N - log N maximum intercell delay, but when high locality occurs in the communications, the mean intercell delay decreases to O(1). The problem of how to map processors with a known traffic distribution onto the terminals of the network in order to minimize the mean intercell delay is analyzed and formulated as a quadratic assignment problem. The uses of this network as a partitioner, a permuter, a full switch and a generalized connection network is discussed.
|Number of pages||5|
|Publication status||Published - 1989|
|Event||International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan|
Duration: 1989 May 17 → 1989 May 19
|Other||International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers|
|Period||1989/05/17 → 1989/05/19|
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