General interconnection network with the consideration of locality in traffic

Shun Shii Lin, Ferng Ching Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A general interconnection network is proposed, taking into account locality of traffic. The network has log2N - log N maximum intercell delay, but when high locality occurs in the communications, the mean intercell delay decreases to O(1). The problem of how to map processors with a known traffic distribution onto the terminals of the network in order to minimize the mean intercell delay is analyzed and formulated as a quadratic assignment problem. The uses of this network as a partitioner, a permuter, a full switch and a generalized connection network is discussed.

Original languageEnglish
Title of host publicationInt Symp VLSI Technol Sys Appl Proc Tech Pap
Editors Anon
PublisherPubl by IEEE
Pages297-301
Number of pages5
Publication statusPublished - 1989
Externally publishedYes
EventInternational Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan
Duration: 1989 May 171989 May 19

Other

OtherInternational Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers
CityTaipei, Taiwan
Period89/5/1789/5/19

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Lin, S. S., & Lin, F. C. (1989). General interconnection network with the consideration of locality in traffic. In Anon (Ed.), Int Symp VLSI Technol Sys Appl Proc Tech Pap (pp. 297-301). Publ by IEEE.