Gate-to-source ESD protection design for GaN-on-silicon power HEMT

Chieh Chen Ker; Chun Yu Lin; Ming Duo Ker; Yu Hsuan Chang; Ching Wei Li; Tsung Yin Chiang; Chun Chi Wang

doi:10.1016/j.microrel.2025.115948

Gate-to-source ESD protection design for GaN-on-silicon power HEMT

Chieh Chen Ker
, Chun Yu Lin
, Ming Duo Ker^*
, Yu Hsuan Chang
, Ching Wei Li
, Tsung Yin Chiang
, Chun Chi Wang

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

A monolithic integrated bidirectional gate-to-source ESD protection circuit for power high-electron-mobility transistor (HEMT) in GaN-on-Si process is proposed. The proposed circuit is incorporated with a voltage detection mechanism to ensure that the ESD protection circuit is selectively activated only under ESD stress conditions, thereby minimizing the unwanted interference and standby leakage current during normal device operation. It has been demonstrated that the proposed design can significantly enhance the robustness against ESD events with human-body-model (HBM) ESD level exceeding ±8 kV and IEC ESD level beyond ±2.5 kV.

Original language	English
Article number	115948
Journal	Microelectronics Reliability
Volume	175
DOIs	https://doi.org/10.1016/j.microrel.2025.115948
Publication status	Published - 2025 Dec
Externally published	Yes

Keywords

ESD protection circuit
Electrostatic discharge (ESD)
Enhancement-mode HEMT
GaN-on-Si process

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Safety, Risk, Reliability and Quality
Condensed Matter Physics
Surfaces, Coatings and Films
Electrical and Electronic Engineering

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10.1016/j.microrel.2025.115948

Cite this

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title = "Gate-to-source ESD protection design for GaN-on-silicon power HEMT",

abstract = "A monolithic integrated bidirectional gate-to-source ESD protection circuit for power high-electron-mobility transistor (HEMT) in GaN-on-Si process is proposed. The proposed circuit is incorporated with a voltage detection mechanism to ensure that the ESD protection circuit is selectively activated only under ESD stress conditions, thereby minimizing the unwanted interference and standby leakage current during normal device operation. It has been demonstrated that the proposed design can significantly enhance the robustness against ESD events with human-body-model (HBM) ESD level exceeding ±8 kV and IEC ESD level beyond ±2.5 kV.",

keywords = "ESD protection circuit, Electrostatic discharge (ESD), Enhancement-mode HEMT, GaN-on-Si process",

author = "Ker, \{Chieh Chen\} and Lin, \{Chun Yu\} and Ker, \{Ming Duo\} and Chang, \{Yu Hsuan\} and Li, \{Ching Wei\} and Chiang, \{Tsung Yin\} and Wang, \{Chun Chi\}",

note = "Publisher Copyright: {\textcopyright} 2025 Elsevier Ltd.",

year = "2025",

month = dec,

doi = "10.1016/j.microrel.2025.115948",

language = "English",

volume = "175",

journal = "Microelectronics Reliability",

issn = "0026-2714",

publisher = "Elsevier Limited",

}

TY - JOUR

T1 - Gate-to-source ESD protection design for GaN-on-silicon power HEMT

AU - Ker, Chieh Chen

AU - Lin, Chun Yu

AU - Ker, Ming Duo

AU - Chang, Yu Hsuan

AU - Li, Ching Wei

AU - Chiang, Tsung Yin

AU - Wang, Chun Chi

PY - 2025/12

Y1 - 2025/12

N2 - A monolithic integrated bidirectional gate-to-source ESD protection circuit for power high-electron-mobility transistor (HEMT) in GaN-on-Si process is proposed. The proposed circuit is incorporated with a voltage detection mechanism to ensure that the ESD protection circuit is selectively activated only under ESD stress conditions, thereby minimizing the unwanted interference and standby leakage current during normal device operation. It has been demonstrated that the proposed design can significantly enhance the robustness against ESD events with human-body-model (HBM) ESD level exceeding ±8 kV and IEC ESD level beyond ±2.5 kV.

AB - A monolithic integrated bidirectional gate-to-source ESD protection circuit for power high-electron-mobility transistor (HEMT) in GaN-on-Si process is proposed. The proposed circuit is incorporated with a voltage detection mechanism to ensure that the ESD protection circuit is selectively activated only under ESD stress conditions, thereby minimizing the unwanted interference and standby leakage current during normal device operation. It has been demonstrated that the proposed design can significantly enhance the robustness against ESD events with human-body-model (HBM) ESD level exceeding ±8 kV and IEC ESD level beyond ±2.5 kV.

KW - ESD protection circuit

KW - Electrostatic discharge (ESD)

KW - Enhancement-mode HEMT

KW - GaN-on-Si process

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UR - https://www.scopus.com/pages/publications/105021855265#tab=citedBy

U2 - 10.1016/j.microrel.2025.115948

DO - 10.1016/j.microrel.2025.115948

M3 - Article

AN - SCOPUS:105021855265

SN - 0026-2714

VL - 175

JO - Microelectronics Reliability

JF - Microelectronics Reliability

M1 - 115948

ER -

Gate-to-source ESD protection design for GaN-on-silicon power HEMT

Abstract

Keywords

ASJC Scopus subject areas

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