Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack

C. H. Cheng; K. I. Chou; A. Chin

doi:10.1016/j.mee.2013.03.082

Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack

C. H. Cheng^*, K. I. Chou, A. Chin

^*Corresponding author for this work

Department of Mechatronic Engineering

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

We report a self-aligned and gate-first TiLaO/La₂O₃ n-MOSFET with an equivalent oxide thickness (EOT) of 0.57 nm and low threshold voltage (V_t) of 0.3 V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799 kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process.

Original language	English
Pages (from-to)	35-38
Number of pages	4
Journal	Microelectronic Engineering
Volume	109
DOIs	https://doi.org/10.1016/j.mee.2013.03.082
Publication status	Published - 2013

Keywords

Gate first
LaO
Low EOT
TiLaO

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Condensed Matter Physics
Surfaces, Coatings and Films
Electrical and Electronic Engineering

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10.1016/j.mee.2013.03.082

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title = "Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack",

abstract = "We report a self-aligned and gate-first TiLaO/La2O3 n-MOSFET with an equivalent oxide thickness (EOT) of 0.57 nm and low threshold voltage (Vt) of 0.3 V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799 kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process.",

keywords = "Gate first, LaO, Low EOT, TiLaO",

author = "Cheng, {C. H.} and Chou, {K. I.} and A. Chin",

year = "2013",

doi = "10.1016/j.mee.2013.03.082",

language = "English",

volume = "109",

pages = "35--38",

journal = "Microelectronic Engineering",

issn = "0167-9317",

publisher = "Elsevier",

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TY - JOUR

T1 - Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack

AU - Cheng, C. H.

AU - Chou, K. I.

AU - Chin, A.

PY - 2013

Y1 - 2013

N2 - We report a self-aligned and gate-first TiLaO/La2O3 n-MOSFET with an equivalent oxide thickness (EOT) of 0.57 nm and low threshold voltage (Vt) of 0.3 V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799 kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process.

AB - We report a self-aligned and gate-first TiLaO/La2O3 n-MOSFET with an equivalent oxide thickness (EOT) of 0.57 nm and low threshold voltage (Vt) of 0.3 V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799 kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process.

KW - Gate first

KW - LaO

KW - Low EOT

KW - TiLaO

UR - http://www.scopus.com/inward/record.url?scp=84876701579&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84876701579&partnerID=8YFLogxK

U2 - 10.1016/j.mee.2013.03.082

DO - 10.1016/j.mee.2013.03.082

M3 - Article

AN - SCOPUS:84876701579

SN - 0167-9317

VL - 109

SP - 35

EP - 38

JO - Microelectronic Engineering

JF - Microelectronic Engineering

ER -

Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack

Abstract

Keywords

ASJC Scopus subject areas

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