Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack

C. H. Cheng, K. I. Chou, A. Chin

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

We report a self-aligned and gate-first TiLaO/La2O3 n-MOSFET with an equivalent oxide thickness (EOT) of 0.57 nm and low threshold voltage (Vt) of 0.3 V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799 kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process.

Original languageEnglish
Pages (from-to)35-38
Number of pages4
JournalMicroelectronic Engineering
Volume109
DOIs
Publication statusPublished - 2013 Apr 30

Fingerprint

Oxides
field effect transistors
oxides
Titanium
Threshold voltage
threshold voltage
low voltage
Enthalpy
CMOS
titanium
enthalpy
Atoms
Defects
defects
atoms

Keywords

  • Gate first
  • LaO
  • Low EOT
  • TiLaO

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

Cite this

Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack. / Cheng, C. H.; Chou, K. I.; Chin, A.

In: Microelectronic Engineering, Vol. 109, 30.04.2013, p. 35-38.

Research output: Contribution to journalArticle

Cheng, C. H. ; Chou, K. I. ; Chin, A. / Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack. In: Microelectronic Engineering. 2013 ; Vol. 109. pp. 35-38.
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