Fractional full-search motion estimation VLSI architecture for H.264/AVC

Chien M. Ou, Huang Chun Roan, Wen J. Hwang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel half-pel full-search motion estimation VLSI architecture for H.264/AVC video encoders is presented in this paper. Based on the processing element arrays eliminating redundant data accesses and attaining 100 % utilization, the architecture can be implemented with low clock rate while having high processing throughput. Such an implementation is particularly suited to applications requiring real time operations with high compression efficiency and low power.

Original languageEnglish
Title of host publicationAdvances in Image and Video Technology - First Pacific Rim Symposium, PSIVT 2006, Proceedings
Pages861-868
Number of pages8
Volume4319 LNCS
DOIs
Publication statusPublished - 2006
Event1st Pacific Rim Symposium on Image and Video Technology, PSIVT 2006 - Hsinchu, Taiwan
Duration: 2006 Dec 102006 Dec 13

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4319 LNCS
ISSN (Print)03029743
ISSN (Electronic)16113349

Other

Other1st Pacific Rim Symposium on Image and Video Technology, PSIVT 2006
CountryTaiwan
CityHsinchu
Period06/12/1006/12/13

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Keywords

  • Fractional motion estimation
  • H.264 standard
  • Video coding
  • VLSI architecture

ASJC Scopus subject areas

  • Computer Science(all)
  • Theoretical Computer Science

Cite this

Ou, C. M., Roan, H. C., & Hwang, W. J. (2006). Fractional full-search motion estimation VLSI architecture for H.264/AVC. In Advances in Image and Video Technology - First Pacific Rim Symposium, PSIVT 2006, Proceedings (Vol. 4319 LNCS, pp. 861-868). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4319 LNCS). https://doi.org/10.1007/11949534-86