FPGA platform for CPU design and applications

Chi Jeng Chang*, Chi Wu Huang, Ying Ping Lin, Zen Yi Huang, Teng Kuei Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)


This paper presents a CPU design of 25 MIPS instructions in addition to the interface controller circuitries of LCD, 7-sequment and key pad and all are downloaded on a 200k gate-count FPGA board for system verification. Then an image process device developed in another FPGA board was connected to the CPU as an image accelerator. By using the same way, other mechantronic or nano devices could also be connected to the CPU with proper designed controllers. The FPGA board could be used for teaching CPU design, controlling applications and also for system-on-chip (SoC) designing since all circuitries might be incorporated in a signal FPGA chip. A multifunctional platform is gradually evolving for teaching and applications.

Original languageEnglish
Title of host publication2005 5th IEEE Conference on Nanotechnology
Number of pages4
Publication statusPublished - 2005
Event2005 5th IEEE Conference on Nanotechnology - Nagoya, Japan
Duration: 2005 Jul 112005 Jul 15

Publication series

Name2005 5th IEEE Conference on Nanotechnology


Other2005 5th IEEE Conference on Nanotechnology


  • CMOS Image Sensor
  • CPU
  • FPGA
  • MIPS
  • SoC

ASJC Scopus subject areas

  • General Engineering


Dive into the research topics of 'FPGA platform for CPU design and applications'. Together they form a unique fingerprint.

Cite this