FPGA platform for CPU design and applications

Chi Jeng Chang; Chi Wu Huang; Ying Ping Lin; Zen Yi Huang; Teng Kuei Hu

FPGA platform for CPU design and applications

Chi Jeng Chang^*, Chi Wu Huang, Ying Ping Lin, Zen Yi Huang, Teng Kuei Hu

^*Corresponding author for this work

Department of Industrial Education

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper presents a CPU design of 25 MIPS instructions in addition to the interface controller circuitries of LCD, 7-sequment and key pad and all are downloaded on a 200k gate-count FPGA board for system verification. Then an image process device developed in another FPGA board was connected to the CPU as an image accelerator. By using the same way, other mechantronic or nano devices could also be connected to the CPU with proper designed controllers. The FPGA board could be used for teaching CPU design, controlling applications and also for system-on-chip (SoC) designing since all circuitries might be incorporated in a signal FPGA chip. A multifunctional platform is gradually evolving for teaching and applications.

Original language	English
Title of host publication	2005 5th IEEE Conference on Nanotechnology
Pages	357-360
Number of pages	4
Publication status	Published - 2005
Event	2005 5th IEEE Conference on Nanotechnology - Nagoya, Japan Duration: 2005 Jul 11 → 2005 Jul 15

Publication series

Name	2005 5th IEEE Conference on Nanotechnology
Volume	1

Other

Other	2005 5th IEEE Conference on Nanotechnology
Country/Territory	Japan
City	Nagoya
Period	2005/07/11 → 2005/07/15

Keywords

CMOS Image Sensor
CPU
FPGA
MIPS
SoC

ASJC Scopus subject areas

General Engineering

Cite this

@inproceedings{7d431ca68a6741c78a21564df1a0a20a,

title = "FPGA platform for CPU design and applications",

abstract = "This paper presents a CPU design of 25 MIPS instructions in addition to the interface controller circuitries of LCD, 7-sequment and key pad and all are downloaded on a 200k gate-count FPGA board for system verification. Then an image process device developed in another FPGA board was connected to the CPU as an image accelerator. By using the same way, other mechantronic or nano devices could also be connected to the CPU with proper designed controllers. The FPGA board could be used for teaching CPU design, controlling applications and also for system-on-chip (SoC) designing since all circuitries might be incorporated in a signal FPGA chip. A multifunctional platform is gradually evolving for teaching and applications.",

keywords = "CMOS Image Sensor, CPU, FPGA, MIPS, SoC",

author = "Chang, {Chi Jeng} and Huang, {Chi Wu} and Lin, {Ying Ping} and Huang, {Zen Yi} and Hu, {Teng Kuei}",

year = "2005",

language = "English",

isbn = "0780391993",

series = "2005 5th IEEE Conference on Nanotechnology",

pages = "357--360",

booktitle = "2005 5th IEEE Conference on Nanotechnology",

note = "2005 5th IEEE Conference on Nanotechnology ; Conference date: 11-07-2005 Through 15-07-2005",

}

TY - GEN

T1 - FPGA platform for CPU design and applications

AU - Chang, Chi Jeng

AU - Huang, Chi Wu

AU - Lin, Ying Ping

AU - Huang, Zen Yi

AU - Hu, Teng Kuei

PY - 2005

Y1 - 2005

N2 - This paper presents a CPU design of 25 MIPS instructions in addition to the interface controller circuitries of LCD, 7-sequment and key pad and all are downloaded on a 200k gate-count FPGA board for system verification. Then an image process device developed in another FPGA board was connected to the CPU as an image accelerator. By using the same way, other mechantronic or nano devices could also be connected to the CPU with proper designed controllers. The FPGA board could be used for teaching CPU design, controlling applications and also for system-on-chip (SoC) designing since all circuitries might be incorporated in a signal FPGA chip. A multifunctional platform is gradually evolving for teaching and applications.

AB - This paper presents a CPU design of 25 MIPS instructions in addition to the interface controller circuitries of LCD, 7-sequment and key pad and all are downloaded on a 200k gate-count FPGA board for system verification. Then an image process device developed in another FPGA board was connected to the CPU as an image accelerator. By using the same way, other mechantronic or nano devices could also be connected to the CPU with proper designed controllers. The FPGA board could be used for teaching CPU design, controlling applications and also for system-on-chip (SoC) designing since all circuitries might be incorporated in a signal FPGA chip. A multifunctional platform is gradually evolving for teaching and applications.

KW - CMOS Image Sensor

KW - CPU

KW - FPGA

KW - MIPS

KW - SoC

UR - http://www.scopus.com/inward/record.url?scp=33746994132&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33746994132&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:33746994132

SN - 0780391993

SN - 9780780391994

T3 - 2005 5th IEEE Conference on Nanotechnology

SP - 357

EP - 360

BT - 2005 5th IEEE Conference on Nanotechnology

T2 - 2005 5th IEEE Conference on Nanotechnology

Y2 - 11 July 2005 through 15 July 2005

ER -

FPGA platform for CPU design and applications

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this