Abstract
This paper presents a CPU design of 25 MIPS instructions in addition to the interface controller circuitries of LCD, 7-sequment and key pad and all are downloaded on a 200k gate-count FPGA board for system verification. Then an image process device developed in another FPGA board was connected to the CPU as an image accelerator. By using the same way, other mechantronic or nano devices could also be connected to the CPU with proper designed controllers. The FPGA board could be used for teaching CPU design, controlling applications and also for system-on-chip (SoC) designing since all circuitries might be incorporated in a signal FPGA chip. A multifunctional platform is gradually evolving for teaching and applications.
| Original language | English |
|---|---|
| Title of host publication | 2005 5th IEEE Conference on Nanotechnology |
| Pages | 357-360 |
| Number of pages | 4 |
| Volume | 1 |
| Publication status | Published - 2005 |
| Event | 2005 5th IEEE Conference on Nanotechnology - Nagoya, Japan Duration: 2005 Jul 11 → 2005 Jul 15 |
Other
| Other | 2005 5th IEEE Conference on Nanotechnology |
|---|---|
| Country | Japan |
| City | Nagoya |
| Period | 05/7/11 → 05/7/15 |
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Keywords
- CMOS Image Sensor
- CPU
- FPGA
- MIPS
- SoC
ASJC Scopus subject areas
- Engineering(all)
Cite this
FPGA platform for CPU design and applications. / Chang, Chi Jeng; Huang, Chi Wu; Lin, Ying Ping; Huang, Zen Yi; Hu, Teng Kuei.
2005 5th IEEE Conference on Nanotechnology. Vol. 1 2005. p. 357-360 1500725.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - FPGA platform for CPU design and applications
AU - Chang, Chi Jeng
AU - Huang, Chi Wu
AU - Lin, Ying Ping
AU - Huang, Zen Yi
AU - Hu, Teng Kuei
PY - 2005
Y1 - 2005
N2 - This paper presents a CPU design of 25 MIPS instructions in addition to the interface controller circuitries of LCD, 7-sequment and key pad and all are downloaded on a 200k gate-count FPGA board for system verification. Then an image process device developed in another FPGA board was connected to the CPU as an image accelerator. By using the same way, other mechantronic or nano devices could also be connected to the CPU with proper designed controllers. The FPGA board could be used for teaching CPU design, controlling applications and also for system-on-chip (SoC) designing since all circuitries might be incorporated in a signal FPGA chip. A multifunctional platform is gradually evolving for teaching and applications.
AB - This paper presents a CPU design of 25 MIPS instructions in addition to the interface controller circuitries of LCD, 7-sequment and key pad and all are downloaded on a 200k gate-count FPGA board for system verification. Then an image process device developed in another FPGA board was connected to the CPU as an image accelerator. By using the same way, other mechantronic or nano devices could also be connected to the CPU with proper designed controllers. The FPGA board could be used for teaching CPU design, controlling applications and also for system-on-chip (SoC) designing since all circuitries might be incorporated in a signal FPGA chip. A multifunctional platform is gradually evolving for teaching and applications.
KW - CMOS Image Sensor
KW - CPU
KW - FPGA
KW - MIPS
KW - SoC
UR - http://www.scopus.com/inward/record.url?scp=33746994132&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33746994132&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:33746994132
SN - 0780391993
SN - 9780780391994
VL - 1
SP - 357
EP - 360
BT - 2005 5th IEEE Conference on Nanotechnology
ER -