FPGA platform for CPU design and applications

Chi Jeng Chang, Chi Wu Huang, Ying Ping Lin, Zen Yi Huang, Teng Kuei Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents a CPU design of 25 MIPS instructions in addition to the interface controller circuitries of LCD, 7-sequment and key pad and all are downloaded on a 200k gate-count FPGA board for system verification. Then an image process device developed in another FPGA board was connected to the CPU as an image accelerator. By using the same way, other mechantronic or nano devices could also be connected to the CPU with proper designed controllers. The FPGA board could be used for teaching CPU design, controlling applications and also for system-on-chip (SoC) designing since all circuitries might be incorporated in a signal FPGA chip. A multifunctional platform is gradually evolving for teaching and applications.

Original languageEnglish
Title of host publication2005 5th IEEE Conference on Nanotechnology
Pages357-360
Number of pages4
Volume1
Publication statusPublished - 2005
Event2005 5th IEEE Conference on Nanotechnology - Nagoya, Japan
Duration: 2005 Jul 112005 Jul 15

Other

Other2005 5th IEEE Conference on Nanotechnology
CountryJapan
CityNagoya
Period05/7/1105/7/15

Fingerprint

Program processors
Field programmable gate arrays (FPGA)
Teaching
Controllers
Liquid crystal displays
Particle accelerators

Keywords

  • CMOS Image Sensor
  • CPU
  • FPGA
  • MIPS
  • SoC

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Chang, C. J., Huang, C. W., Lin, Y. P., Huang, Z. Y., & Hu, T. K. (2005). FPGA platform for CPU design and applications. In 2005 5th IEEE Conference on Nanotechnology (Vol. 1, pp. 357-360). [1500725]

FPGA platform for CPU design and applications. / Chang, Chi Jeng; Huang, Chi Wu; Lin, Ying Ping; Huang, Zen Yi; Hu, Teng Kuei.

2005 5th IEEE Conference on Nanotechnology. Vol. 1 2005. p. 357-360 1500725.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chang, CJ, Huang, CW, Lin, YP, Huang, ZY & Hu, TK 2005, FPGA platform for CPU design and applications. in 2005 5th IEEE Conference on Nanotechnology. vol. 1, 1500725, pp. 357-360, 2005 5th IEEE Conference on Nanotechnology, Nagoya, Japan, 05/7/11.
Chang CJ, Huang CW, Lin YP, Huang ZY, Hu TK. FPGA platform for CPU design and applications. In 2005 5th IEEE Conference on Nanotechnology. Vol. 1. 2005. p. 357-360. 1500725
Chang, Chi Jeng ; Huang, Chi Wu ; Lin, Ying Ping ; Huang, Zen Yi ; Hu, Teng Kuei. / FPGA platform for CPU design and applications. 2005 5th IEEE Conference on Nanotechnology. Vol. 1 2005. pp. 357-360
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