FPGA implementation of kNN classifier based on wavelet transform and partial distance search

Yao Jung Yen, Hui Y. Li, Wen J. Hwang, Chiung Y. Fang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)


A novel algorithm for field programmable gate array (FPGA) realization of kNN classifier is presented in this paper. The algorithm identifies first k closest vectors in the design set of a kNN classifier for each input vector by performing the partial distance search (PDS) in the wavelet domain. It employs subspace search, bitplane reduction and multiple-coefficient accumulation techniques for the effective reduction of the area complexity and computation latency. The proposed implementation has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the implementation provides a cost-effective solution to the FPGA realization of kNN classification systems where both high throughput and low area cost are desired.

Original languageEnglish
Title of host publicationImage Analysis - 15th Scandinavian Conference, SCIA 2007, Proceedings
Number of pages10
Volume4522 LNCS
Publication statusPublished - 2007
Event15th Scandinavian Conference on Image Analysis, SCIA 2007 - Aalborg, Denmark
Duration: 2007 Jun 102007 Jun 14

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4522 LNCS
ISSN (Print)03029743
ISSN (Electronic)16113349


Other15th Scandinavian Conference on Image Analysis, SCIA 2007


  • FPGA implementation
  • Image processing
  • Nonparametric classification
  • Partial distance search
  • Pattern recognition

ASJC Scopus subject areas

  • Computer Science(all)
  • Biochemistry, Genetics and Molecular Biology(all)
  • Theoretical Computer Science


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