FPGA implementation of full-search vector quantization based on partial distance search

Wen Jyi Hwang*, Wen Kang Wei, Yao Jung Yeh

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)


This paper presents a novel algorithm for field programmable gate array (FPGA) realization of vector quantizer (VQ) encoders using partial distance search (PDS). In most applications, the PDS is adopted as a software approach for attaining moderate codeword search acceleration. In this paper, a novel PDS algorithm well suited for hardware realization is proposed. The algorithm employs subspace search, bitplane reduction, and multiple-coefficient accumulation techniques for the effective reduction of the area complexity and computation latency. Concurrent encoding of different input vectors for further computation acceleration is also allowed by the employment of multiple-module PDS. The proposed implementation has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the implementation provides a cost-effective solution to the FPGA realization of VQ encoding systems where both high throughput and high fidelity are desired.

Original languageEnglish
Pages (from-to)516-528
Number of pages13
JournalMicroprocessors and Microsystems
Issue number8
Publication statusPublished - 2007 Dec 3


  • FPGA implementation
  • Partial distance search
  • Softcore CPU
  • Vector quantization

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence


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