Fpga design of enhanced scale-invariant feature transform with finite-area parallel feature matching for stereo vision

Chien Hung Kuo, Erh Hsu Huang, Chiang Heng Chien, Chen Chien Hsu*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


In this paper, we propose an FPGA-based enhanced-SIFT with feature matching for stereo vision. Gaussian blur and difference of Gaussian pyramids are realized in parallel to accelerate the processing time required for multiple convolutions. As for the feature descriptor, a simple triangu-lar identification approach with a look-up table is proposed to efficiently determine the direction and gradient of the feature points. Thus, the dimension of the feature descriptor in this paper is reduced by half compared to conventional approaches. As far as feature detection is concerned, the condition for high-contrast detection is simplified by moderately changing a threshold value, which also benefits the reduction of the resulting hardware in realization. The proposed enhanced-SIFT not only accelerates the operational speed but also reduces the hardware cost. The experiment re-sults show that the proposed enhanced-SIFT reaches a frame rate of 205 fps for 640 × 480 images. Integrated with two enhanced-SIFT, a finite-area parallel checking is also proposed without the aid of external memory to improve the efficiency of feature matching. The resulting frame rate by the proposed stereo vision matching can be as high as 181 fps with good matching accuracy as demon-strated in the experimental results.

Original languageEnglish
Article number1632
JournalElectronics (Switzerland)
Issue number14
Publication statusPublished - 2021 Jul 2


  • Epipolar
  • FPGA
  • Feature descriptor
  • Feature detection
  • Feature matching
  • SIFT
  • Stereo vision

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Signal Processing
  • Hardware and Architecture
  • Computer Networks and Communications
  • Electrical and Electronic Engineering


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