FPGA-based hardware design for scale-invariant feature transform

Shih An Li, Wei Yen Wang, Wei Zheng Pan, Chen Chien James Hsu, Cheng Kai Lu

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper proposes a novel hardware design method of scale-invariant feature transform (SIFT) algorithm for implementation on field-programmable gate array (FPGA). To reduce the computing costs, Gaussian kernels are calculated offline for use in Gaussian filters. To eliminate low-contrast points, the inverse of a Hessian matrix is required for hardware implementation, which results in poor performance because dividers are needed. To solve this problem, this paper presents a new mathematical derivation model to implement the low-contrast detection, avoiding the use of any dividers. For the implementation of the normalization module, a large number of dividers are required by traditional methods, which adversely affects the computational efficiency. This paper presents a new architecture using only one divider to implement the normalization function in hardware. Thanks to the parallel processing architecture proposed to design the image pyramid, SIFT detection, and SIFT descriptor, the computational efficiency of the SIFT algorithm is significantly improved. As a result of the proposed design method, the requirement of logic elements in the FPGA hardware is greatly reduced and system frequency is significantly increased. Experimental results show that the proposed hardware architecture outperforms existing techniques in terms of resource usage and computational efficiency for real-time image processing.

Original languageEnglish
Article number8425023
Pages (from-to)43850-43864
Number of pages15
JournalIEEE Access
Volume6
DOIs
Publication statusPublished - 2018 Aug 3

Fingerprint

Field programmable gate arrays (FPGA)
Hardware
Computational efficiency
Image processing
Mathematical models
Processing
Costs

Keywords

  • field-programmable gate array
  • parallel processing architecture
  • Scale-invariant feature transform

ASJC Scopus subject areas

  • Computer Science(all)
  • Materials Science(all)
  • Engineering(all)

Cite this

FPGA-based hardware design for scale-invariant feature transform. / Li, Shih An; Wang, Wei Yen; Pan, Wei Zheng; Hsu, Chen Chien James; Lu, Cheng Kai.

In: IEEE Access, Vol. 6, 8425023, 03.08.2018, p. 43850-43864.

Research output: Contribution to journalArticle

Li, Shih An ; Wang, Wei Yen ; Pan, Wei Zheng ; Hsu, Chen Chien James ; Lu, Cheng Kai. / FPGA-based hardware design for scale-invariant feature transform. In: IEEE Access. 2018 ; Vol. 6. pp. 43850-43864.
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