First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles

Yu Rui Chen*, Yi Chun Liu, Zefu Zhao, Wan Hsuan Hsieh, Jia Yang Lee, Chien Te Tu, Bo Wei Huang, Jer Fu Wang, Shee Jier Chueh, Yifan Xing, Guan Hua Chen, Hung Chun Chou, Dong Soo Woo, M. H. Lee, C. W. Liu*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The large memory window of 1.8V at the low write voltage of 2V is achieved by stacked two nanosheet (NS) gate-allaround (GAA) Ge0.98Si0.02 FeFETs with the channel phosphorus concentration larger than 1E18cm-3, enabling the erase of GAA FeFET. Isotropic wet etching was used in channel release process. Stacked two NSs have the advantages of reducing cell variation and 2X read current. The stable storage with data retention of > 1E4 seconds, linearly extrapolated 10 years, and high endurance > 1E11 cycles are also demonstrated. The thermal budget is as low as 400°C. The stacked NS architecture with high mobility channels makes FeFETs to be compatible with the 2nm node and beyond.

Original languageEnglish
Title of host publication2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863488069
DOIs
Publication statusPublished - 2023
Externally publishedYes
Event2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan
Duration: 2023 Jun 112023 Jun 16

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2023-June
ISSN (Print)0743-1562

Conference

Conference2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/TerritoryJapan
CityKyoto
Period2023/06/112023/06/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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