First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles

Yu Rui Chen; Yi Chun Liu; Zefu Zhao; Wan Hsuan Hsieh; Jia Yang Lee; Chien Te Tu; Bo Wei Huang; Jer Fu Wang; Shee Jier Chueh; Yifan Xing; Guan Hua Chen; Hung Chun Chou; Dong Soo Woo; M. H. Lee; C. W. Liu

doi:10.23919/VLSITechnologyandCir57934.2023.10185284

First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles

Yu Rui Chen^*, Yi Chun Liu, Zefu Zhao, Wan Hsuan Hsieh, Jia Yang Lee, Chien Te Tu, Bo Wei Huang, Jer Fu Wang, Shee Jier Chueh, Yifan Xing, Guan Hua Chen, Hung Chun Chou, Dong Soo Woo, M. H. Lee, C. W. Liu^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

The large memory window of 1.8V at the low write voltage of 2V is achieved by stacked two nanosheet (NS) gate-allaround (GAA) Ge0.98Si0.02 FeFETs with the channel phosphorus concentration larger than 1E18cm-3, enabling the erase of GAA FeFET. Isotropic wet etching was used in channel release process. Stacked two NSs have the advantages of reducing cell variation and 2X read current. The stable storage with data retention of > 1E4 seconds, linearly extrapolated 10 years, and high endurance > 1E11 cycles are also demonstrated. The thermal budget is as low as 400°C. The stacked NS architecture with high mobility channels makes FeFETs to be compatible with the 2nm node and beyond.

Original language	English
Title of host publication	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863488069
DOIs	https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185284
Publication status	Published - 2023
Externally published	Yes
Event	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan Duration: 2023 Jun 11 → 2023 Jun 16

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2023-June
ISSN (Print)	0743-1562

Conference

Conference	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/Territory	Japan
City	Kyoto
Period	2023/06/11 → 2023/06/16

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.23919/VLSITechnologyandCir57934.2023.10185284

Cite this

Chen, Y. R., Liu, Y. C., Zhao, Z., Hsieh, W. H., Lee, J. Y., Tu, C. T., Huang, B. W., Wang, J. F., Chueh, S. J., Xing, Y., Chen, G. H., Chou, H. C., Woo, D. S., Lee, M. H., & Liu, C. W. (2023). First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2023-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185284

First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles. / Chen, Yu Rui; Liu, Yi Chun; Zhao, Zefu et al.
2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2023-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chen, YR, Liu, YC, Zhao, Z, Hsieh, WH, Lee, JY, Tu, CT, Huang, BW, Wang, JF, Chueh, SJ, Xing, Y, Chen, GH, Chou, HC, Woo, DS, Lee, MH & Liu, CW 2023, First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles. in 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2023-June, Institute of Electrical and Electronics Engineers Inc., 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023, Kyoto, Japan, 2023/06/11. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185284

Chen YR, Liu YC, Zhao Z, Hsieh WH, Lee JY, Tu CT et al. First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSITechnologyandCir57934.2023.10185284

Chen, Yu Rui ; Liu, Yi Chun ; Zhao, Zefu et al. / First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles. 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology).

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title = "First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles",

abstract = "The large memory window of 1.8V at the low write voltage of 2V is achieved by stacked two nanosheet (NS) gate-allaround (GAA) Ge0.98Si0.02 FeFETs with the channel phosphorus concentration larger than 1E18cm-3, enabling the erase of GAA FeFET. Isotropic wet etching was used in channel release process. Stacked two NSs have the advantages of reducing cell variation and 2X read current. The stable storage with data retention of > 1E4 seconds, linearly extrapolated 10 years, and high endurance > 1E11 cycles are also demonstrated. The thermal budget is as low as 400°C. The stacked NS architecture with high mobility channels makes FeFETs to be compatible with the 2nm node and beyond.",

author = "Chen, {Yu Rui} and Liu, {Yi Chun} and Zefu Zhao and Hsieh, {Wan Hsuan} and Lee, {Jia Yang} and Tu, {Chien Te} and Huang, {Bo Wei} and Wang, {Jer Fu} and Chueh, {Shee Jier} and Yifan Xing and Chen, {Guan Hua} and Chou, {Hung Chun} and Woo, {Dong Soo} and Lee, {M. H.} and Liu, {C. W.}",

note = "Publisher Copyright: {\textcopyright} 2023 JSAP.; 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 ; Conference date: 11-06-2023 Through 16-06-2023",

year = "2023",

doi = "10.23919/VLSITechnologyandCir57934.2023.10185284",

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AU - Zhao, Zefu

AU - Hsieh, Wan Hsuan

AU - Lee, Jia Yang

AU - Tu, Chien Te

AU - Huang, Bo Wei

AU - Wang, Jer Fu

AU - Chueh, Shee Jier

AU - Xing, Yifan

AU - Chen, Guan Hua

AU - Chou, Hung Chun

AU - Woo, Dong Soo

AU - Lee, M. H.

AU - Liu, C. W.

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AB - The large memory window of 1.8V at the low write voltage of 2V is achieved by stacked two nanosheet (NS) gate-allaround (GAA) Ge0.98Si0.02 FeFETs with the channel phosphorus concentration larger than 1E18cm-3, enabling the erase of GAA FeFET. Isotropic wet etching was used in channel release process. Stacked two NSs have the advantages of reducing cell variation and 2X read current. The stable storage with data retention of > 1E4 seconds, linearly extrapolated 10 years, and high endurance > 1E11 cycles are also demonstrated. The thermal budget is as low as 400°C. The stacked NS architecture with high mobility channels makes FeFETs to be compatible with the 2nm node and beyond.

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First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles

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