First demonstration of flash RRAM on pure CMOS logic 14nm FinFET platform featuring excellent immunity to sneak-path and MLC capability

E. R. Hsieh, Y. C. Kuo, C. H. Cheng, J. L. Kuo, M. R. Jiang, J. L. Lin, H. W. Cheng, Steve S. Chung, C. H. Liu, T. P. Chen, Y. H. Yeah, T. J. Chen, Osbert Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

For the first time, the ion-vacancy-based bipolar RRAM has been demonstrated on HKMG stack of FEOL logic 14nm FinFET. A unit cell with two identical FinFETs, one serves as a control transistor and the other one is the storage with resistance switching. It is performed by the edge tunneling and with bipolar switching. More importantly, the sneak path issue in an AND-type array based on this FinFET unit cell has been thoroughly investigated. To solve sneak path issue, a new active-fin-isolation (AFI) of FinFET in an AND-type array was proposed. This new AFI effectively increases the S/N margin of 103 and significantly reduces the standby power of 30% and active power of 99%, compared to original AND-type array. This work provides a promising candidate for the embedded FLASH memory on FinFET platform featuring fully-CMOS compatible integration and low cost solution in the more-than-Moore era.

Original languageEnglish
Title of host publication2017 Symposium on VLSI Technology, VLSI Technology 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesT72-T73
ISBN (Electronic)9784863486058
DOIs
Publication statusPublished - 2017 Jul 31
Event37th Symposium on VLSI Technology, VLSI Technology 2017 - Kyoto, Japan
Duration: 2017 Jun 52017 Jun 8

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference37th Symposium on VLSI Technology, VLSI Technology 2017
CountryJapan
CityKyoto
Period17/6/517/6/8

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Hsieh, E. R., Kuo, Y. C., Cheng, C. H., Kuo, J. L., Jiang, M. R., Lin, J. L., Cheng, H. W., Chung, S. S., Liu, C. H., Chen, T. P., Yeah, Y. H., Chen, T. J., & Cheng, O. (2017). First demonstration of flash RRAM on pure CMOS logic 14nm FinFET platform featuring excellent immunity to sneak-path and MLC capability. In 2017 Symposium on VLSI Technology, VLSI Technology 2017 (pp. T72-T73). [7998204] (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2017.7998204