Ferroelectric HZO (ferroelectric-Hf₁₋ₓZrₓO₂) FETs on SOI (silicon on insulator) are modeled and demonstrated with improvement on subthreshold swing (SS) and hysteresis (VT-shift), which is based on the capacitance matching concept. The minimum reverse SS = 45 mV/dec and 52 mV/dec are obtained experimentally for SOI and bulk-Si, respectively. The steep SS range (<60 mV/dec) is extended from ∼2.5 (bulk-Si) decades to ∼3.5 decades (SOI). Reverse-DIBL (drain-induced barrier lowering) and NDR (negative differential resistance) are confirmed at subthreshold region and weak inversion region, respectively.
- Field effect transistors
- Load modeling
- Logic gates
- Negative Differential Resistance.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering