Fast principal component analysis based on hardware architecture of generalized hebbian algorithm

Shiow Jyu Lin*, Yi Tsan Hung, Wen Jyi Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents a novel hardware architecture for fast principle component analysis (PCA). The architecture is developed based on generalized Hebbian algorithm (GHA). In the architecture, the updating of different synaptic weight vectors are divided into a number of stages. The results of precedent stages are used for the computation of subsequent stages for expediting training speed and lowering the area cost. The proposed architecture has been embedded in a system-on-programmable-chip (SOPC) platform for physical performance measurement. Experimental results show that the proposed architecture is an effective alternative for fast PCA in attaining both high performance and low computation time.

Original languageEnglish
Title of host publicationAdvances in Computation and Intelligence - 5th International Symposium, ISICA 2010, Proceedings
Pages505-515
Number of pages11
EditionM4D
DOIs
Publication statusPublished - 2010
Event5th International Symposium on Advances in Computation and Intelligence, ISICA 2010 - Wuhan, China
Duration: 2010 Oct 222010 Oct 24

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
NumberM4D
Volume6382 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other5th International Symposium on Advances in Computation and Intelligence, ISICA 2010
Country/TerritoryChina
CityWuhan
Period2010/10/222010/10/24

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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